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Integration density limitation in 3D integrated circuits due to heat dissipationGHIBAUDO, G; JAOUEN, H; KAMARINOS, G et al.Europhysics letters (Print). 1986, Vol 2, Num 3, pp 209-211, issn 0295-5075Article

Cost-density analysis of interconnectionsMESSNER, G.IEEE transactions on components, hybrids, and manufacturing technology. 1987, Vol 10, Num 2, pp 143-151, issn 0148-6411Article

Short-term forecasting in electronicsMILOJKOVIC, Jelena; LITOVSKI, Vančo.International journal of electronics. 2011, Vol 98, Num 1-3, pp 161-172, issn 0020-7217, 12 p.Article

Field reduction regions for compact high-voltage IC'sSUGAWARA, Y; KAMEI, T.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 8, pp 1816-1822, issn 0018-9383, 1Article

Le câblage par fil: une nouvelle piste pour les cartes à CMS = The wiring: a new track for SMC boardsMesures (1983). 1987, Vol 52, Num 12, pp 55-61, issn 0755-219X, 4 p.Article

Analysis of the silicon technology roadmap : How far can CMOS go ? : Les défis techniques de la microélectronique = Challenges in microelectronicsSKOTNICKI, Thomas.Comptes rendus de l'Académie des sciences. Série IV, Physique, astrophysique. 2000, Vol 1, Num 7, pp 885-909, issn 1296-2147Article

Algorithm for incremental compaction of geometrical layoutsNANDY, S. K; PATNAIK, L. M.Computer-aided design. 1987, Vol 19, Num 5, pp 257-265, issn 0010-4485Article

LSI layout using hierarchical design with compactionABRAITIS, L; BARILA, A.Computer-aided design. 1986, Vol 18, Num 7, pp 367-370, issn 0010-4485Article

Large-output-force out-of-plane MEMS actuator arrayFUKUSHIGE, T; HATA, S; SHIMOKOHBE, A et al.SPIE proceedings series. 2004, pp 240-249, isbn 0-8194-5169-X, 10 p.Conference Paper

Failure analysis techniques for a 3D worldHENDERSON, Christopher L.Microelectronics and reliability. 2013, Vol 53, Num 9-11, pp 1171-1178, issn 0026-2714, 8 p.Conference Paper

Fifty Years of Moore's LawMACK, Chris A.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 2, pp 202-207, issn 0894-6507, 6 p.Article

Future Directions for CMOS Device Technology Development from a System Application PerspectiveNINE, Tak H.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 652003.1-652003.5, issn 0277-786X, isbn 978-0-8194-6639-6Conference Paper

Trends in IC socket designLEIDY, J.Electri.onics. 1987, Vol 33, Num 9, pp 41-42, issn 0745-4309Article

Scatterometry for EUV lithography at the 22 nm nodeBUNDAY, Benjamin; VARTANIAN, Victor; LIPING REN et al.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 7971, issn 0277-786X, isbn 978-0-8194-8530-4, 797120.1-797120.13, 2Conference Paper

Design Aspects of 3D Integration of MEMS-based SystemsSCHNEIDER, Peter; REITZ, Sven; STOLLE, Jörn et al.Symposium on design, test, integration and packaging of MEMS-MOEMS. 2009, pp 92-97, isbn 978-2-35500-009-6, 1Vol, 6 p.Conference Paper

Damageless FeRAM integration process : Special issue on ferroelectric memory technologyAMANUMA, K; OKIZAKI, H; KOBAYASHI, S et al.NEC research & development. 1999, Vol 40, Num 2, pp 227-230, issn 0547-051XArticle

Tape BGAs satisfy high-end IC demandsGIESLER, M; SCHUELLER, R.Electronic design. 1998, Vol 46, Num 14, pp 154-158, issn 0013-4872, 3 p.Article

A novel 2-D programmable photonic time-delay device for millimeter-wave signal processing applicationsYAO, X. S; MALEKI, L.IEEE photonics technology letters. 1994, Vol 6, Num 12, pp 1463-1465, issn 1041-1135Article

VLSI computations: from physics to algorithmsCARD, H. C.Integration (Amsterdam). 1987, Vol 5, Num 3-4, pp 247-273, issn 0167-9260Article

Gate-Array-Schaltkreise-eine Alternative zu mikroprozessorschaltkreisen? = Circuits sur réseaux prédiffusés à une alternative des microprocesseurs = Gate-array circuits on an alternative to microprocessor circuitsMÜLLER, D.Wissenschaftliche Zeitschrift der Technischen Hochschule Karl-Marx-Stadt. 1985, Vol 27, Num 2, pp 245-251, issn 0372-7610Article

Influence of dicing damages on the thermo-mechanical reliability of bare-chip assembliesSTEIERT, M; WILDE, J.Microelectronics and reliability. 2014, Vol 54, Num 9-10, pp 1686-1691, issn 0026-2714, 6 p.Conference Paper

Two-Dimensional Analysis Photothermal Properties in Nanoscale Plasmonic Waveguides for Optical Interconnect : OPTICAL INTERCONNECTSQIANG LI; WEICHUN ZHANG; HANG ZHAO et al.Journal of lightwave technology. 2013, Vol 31, Num 21-24, pp 4051-4056, issn 0733-8724, 6 p.Article

System-on-chip : A way around lithography limitationsL.BALDI.Microelectronic engineering. 2000, Vol 53, Num 1-4, pp 5-11, issn 0167-9317Conference Paper

Low-IF topologies for high-performance analog front ends of fully integrated receiversCROLS, J; STEYAERT, M. S. J.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1998, Vol 45, Num 3, pp 269-282, issn 1057-7130Article

Module frequency estimation and noise budget limitations/trade-offs in multichip modules as a function of CMOS chips integration : PackagingRAMESH SENTHINATHAN; PRINCE, J. L; CANGELLARIS, A. C et al.IEEE transactions on components, hybrids, and manufacturing technology. 1993, Vol 16, Num 5, pp 478-483, issn 0148-6411Article

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