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Results 1 to 25 of 172

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Novel method for analysis of printed circuit imagesMANDEVILLE, J. R.IBM journal of research and development. 1985, Vol 29, Num 1, pp 73-86, issn 0018-8646Article

Integration density limitation in 3D integrated circuits due to heat dissipationGHIBAUDO, G; JAOUEN, H; KAMARINOS, G et al.Europhysics letters (Print). 1986, Vol 2, Num 3, pp 209-211, issn 0295-5075Article

Short-term forecasting in electronicsMILOJKOVIC, Jelena; LITOVSKI, Vančo.International journal of electronics. 2011, Vol 98, Num 1-3, pp 161-172, issn 0020-7217, 12 p.Article

Trends in developing electrical actuatorsGUTT, H.-J.European transactions on electrical power engineering. 1992, Vol 2, Num 2, pp 69-76, issn 0939-3072Article

Cost-density analysis of interconnectionsMESSNER, G.IEEE transactions on components, hybrids, and manufacturing technology. 1987, Vol 10, Num 2, pp 143-151, issn 0148-6411Article

Field reduction regions for compact high-voltage IC'sSUGAWARA, Y; KAMEI, T.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 8, pp 1816-1822, issn 0018-9383, 1Article

Le câblage par fil: une nouvelle piste pour les cartes à CMS = The wiring: a new track for SMC boardsMesures (1983). 1987, Vol 52, Num 12, pp 55-61, issn 0755-219X, 4 p.Article

Edge-defined self-alignment of submicrometer overlaid devicesMALHI, S. D. S; CHATTERJEE, P. K; BONIFIELD, T. D et al.IEEE electron device letters. 1984, Vol 5, Num 10, pp 428-429, issn 0741-3106Article

Analysis of the silicon technology roadmap : How far can CMOS go ? : Les défis techniques de la microélectronique = Challenges in microelectronicsSKOTNICKI, Thomas.Comptes rendus de l'Académie des sciences. Série IV, Physique, astrophysique. 2000, Vol 1, Num 7, pp 885-909, issn 1296-2147Article

Algorithm for incremental compaction of geometrical layoutsNANDY, S. K; PATNAIK, L. M.Computer-aided design. 1987, Vol 19, Num 5, pp 257-265, issn 0010-4485Article

LSI layout using hierarchical design with compactionABRAITIS, L; BARILA, A.Computer-aided design. 1986, Vol 18, Num 7, pp 367-370, issn 0010-4485Article

Failure analysis techniques for a 3D worldHENDERSON, Christopher L.Microelectronics and reliability. 2013, Vol 53, Num 9-11, pp 1171-1178, issn 0026-2714, 8 p.Conference Paper

Fifty Years of Moore's LawMACK, Chris A.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 2, pp 202-207, issn 0894-6507, 6 p.Article

Future Directions for CMOS Device Technology Development from a System Application PerspectiveNINE, Tak H.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 652003.1-652003.5, issn 0277-786X, isbn 978-0-8194-6639-6Conference Paper

Trends in IC socket designLEIDY, J.Electri.onics. 1987, Vol 33, Num 9, pp 41-42, issn 0745-4309Article

Large-output-force out-of-plane MEMS actuator arrayFUKUSHIGE, T; HATA, S; SHIMOKOHBE, A et al.SPIE proceedings series. 2004, pp 240-249, isbn 0-8194-5169-X, 10 p.Conference Paper

Formal design procedures for pass transistor switching circuitsDAMU RADHAKRISHNAN; WHITAKER, S. R; MAKI, G. K et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 2, pp 531-536, issn 0018-9200Article

Sources of failures and yield improvement for VLSI and restructurable interconnects for RVLSI and WSI. II: Restructurable interconnects for RVLSI and WSIMANGIR, T. E.Proceedings of the IEEE. 1984, Vol 72, Num 12, pp 1687-1694, issn 0018-9219Article

TEXAS INSTRUMENTS VIENT AUX RESEAUX LOGIQUES PREDIFFUSESITICSOHN P.1981; ELECTRON. IND.; FRA; DA. 1981; NO 13; PP. 55-57Article

COMPUTER-AIDED PLACEMENT FOR HIGH-DENSITY CHIP-INTERCONNECTION SYSTEMSCROCKER NR; MCGUFFIN RW; NAYLOR R et al.1972; ELECTRON. LETTERS; G.B.; DA. 1972; VOL. 8; NO 20; PP. 503-504Serial Issue

HIGH-DENSITY AVIONIC POWER SUPPLYHEDEL KK.1980; I.E.E.E. TRANS. AEROSP. ELECTRON. SYST.; ISSN 0018-9251; USA; DA. 1980; VOL. 16; NO 5; PP. 615-619; BIBL. 4 REF.Article

IBM MULTICHIP MULTILAYER CERAMIC MODULES FOR LSI CHIPS - DESIGN FOR PERFORMANCE AND DENSITYCLARK BT; HILL YM.1980; I.E.E.E. TRANS. COMPON. HYBR. MANUFG TECHNOL.; USA; DA. 1980; VOL. 3; NO 1; PP. 89-93; BIBL. 1 REF.Article

THE INTERDEPENDENCE OF GEOMETRICAL, THERMAL, AND ELECTRICAL LIMITATIONS FOR VLSI LOGICFOLBERTH OG.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 1; PP. 51-53; BIBL. 13 REF.Article

AMELIORATION DE LA DENSITE D'INTEGRATION DES CIRCUITS DE GRANDE COMPLEXITE A T MOS SUR SSI.SUAT JP; MONTIER M; GRIS Y et al.1978; DGRST-7670652; FR.; DA. 1978; PP. 1-17; H.T. 18; BIBL. 4 REF.; (RAPP. FINAL, ACTION CONCERTEE: COMPOSANTS CIRCUITS MICROMINIATURISES)Report

TRANSMISSION PROPERTIES OF VARIOUS STYLES OF PRINTED WIRING BOARDSRAINAL AJ.1979; BELL SYST. TECH. J.; USA; DA. 1979; VOL. 58; NO 5; PP. 995-1025; BIBL. 15 REF.Article

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