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Results 1 to 25 of 391

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Modeling of potentials and threshold voltage for symmetric doped double-gate MOSFETsCERDEIRA, A; MOLDOVAN, O; INIGUEZ, B et al.Solid-state electronics. 2008, Vol 52, Num 5, pp 830-837, issn 0038-1101, 8 p.Article

Universal Potential Model in Tied and Separated Double-Gate MOSFETs With Consideration of Symmetric and Asymmetric StructureHAN, Jin-Woo; KIM, Chung-Jin; CHOI, Yang-Kyu et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 6, pp 1472-1479, issn 0018-9383, 8 p.Article

A design oriented charge-based current model for symmetric DG MOSFET and its correlation with the EKV formalismSALLESE, Jean-Michel; KRUMMENACHER, Francois; PREGALDINY, Fabien et al.Solid-state electronics. 2005, Vol 49, Num 3, pp 485-489, issn 0038-1101, 5 p.Article

Tunable contact resistance in double-gate organic field-effect transistorsYONG XU; DARMAWAN, Peter; CHUAN LIU et al.Organic electronics (Print). 2012, Vol 13, Num 9, pp 1583-1588, issn 1566-1199, 6 p.Article

Optimum crystallographic alignment for Si n-Channel ballistic DGFETsLAUX, S. E.IEEE electron device letters. 2005, Vol 26, Num 9, pp 679-681, issn 0741-3106, 3 p.Article

Justifying threshold voltage definition for undoped body transistors through crossover point conceptRATUL KUMAR BARUAH; MAHAPATRA, Santanu.Physica. B, Condensed matter. 2009, Vol 404, Num 8-11, pp 1029-1032, issn 0921-4526, 4 p.Article

Performance Enhancement in Double-Gated Poly-Si Nanowire Transistors With Reduced Nanowire Channel ThicknessLIN, Homg-Chih; CHEN, Wei-Chen; HUANG, Tiao-Yuan et al.IEEE electron device letters. 2009, Vol 30, Num 6, pp 644-646, issn 0741-3106, 3 p.Article

A simple modelling of device speed in double-gate SOI MOSFETsRAJENDRAN, K; SAMUDRA, G.Microelectronics journal. 2000, Vol 31, Num 4, pp 255-259, issn 0959-8324Article

Double-gate silicon-on-insulator transistor with volume inversion: a new device with greatly enhanced performanceBALESTRA, F; CRISTOLOVEANU, S; BENACHIR, M et al.IEEE electron device letters. 1987, Vol 8, Num 9, pp 410-412, issn 0741-3106Article

Form factor increase and its physical origins in electron-modulated acoustic phonon interaction in a free-standing semiconductor plateUNO, Shigeyasu; HATTORI, Junichi; NAKAZATO, Kazuo et al.Mathematical and computer modelling. 2010, Vol 51, Num 7-8, pp 863-872, issn 0895-7177, 10 p.Article

Full quantum treatment of surface roughness effects in Silicon nanowire and double gate FETsPALA, Marco G; BURAN, Claudio; POLI, Stefano et al.Journal of computational electronics (Print). 2009, Vol 8, Num 3-4, pp 374-381, issn 1569-8025, 8 p.Article

Threshold voltages of SOI MuGFETsDE ANDRADE, Maria Gloria Cano; MARTINO, Joao Antonio.Solid-state electronics. 2008, Vol 52, Num 12, pp 1877-1883, issn 0038-1101, 7 p.Conference Paper

Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETsPEICHENG LI; GUANGXI HU; RAN LIU et al.Microelectronics journal. 2011, Vol 42, Num 10, pp 1164-1168, issn 0959-8324, 5 p.Article

High-performance top and bottom double-gate low-temperature poly-silicon thin film transistors fabricated by excimer laser crystallizationTSAI, Chun-Chien; LEE, Yao-Jen; WANG, Jyh-Liang et al.Solid-state electronics. 2008, Vol 52, Num 3, pp 365-371, issn 0038-1101, 7 p.Conference Paper

Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETsHUBERT, A; BAWEDIN, M; CRISTOLOVEANU, S et al.Solid-state electronics. 2009, Vol 53, Num 12, pp 1280-1286, issn 0038-1101, 7 p.Article

A comparison study of symmetric ultrathin-body double-gate devices with metal source/drain and doped source/drainSHIYING XIONG; KING, Tsu-Jae; BOKOR, Jeffrey et al.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 8, pp 1859-1867, issn 0018-9383, 9 p.Article

An analytical symmetric double-gate SOI MOSFET modelJIOU, H.-K; JANG, S.-L; LIU, S.-S et al.International journal of electronics. 1999, Vol 86, Num 6, pp 671-683, issn 0020-7217Article

Enhanced coupling effects in vertical double-gate FinFETsCHANG, Sung-Jae; BAWEDIN, Maryline; YUFENG GUO et al.Solid-state electronics. 2014, Vol 97, pp 88-98, issn 0038-1101, 11 p.Article

A unified analytical continuous current model applicable to accumulation mode (junctionless) and inversion mode MOSFETs with symmetric and asymmetric double-gate structuresXIAOSHI JIN; XI LIU; MEILE WU et al.Solid-state electronics. 2013, Vol 79, pp 206-209, issn 0038-1101, 4 p.Article

A comparative study for quantum transport calculations of nanosized field-effect transistorsJIANG, Xiang-Wei; LI, Shu-Shen; WANG, Lin-Wang et al.Solid-state electronics. 2012, Vol 68, pp 56-62, issn 0038-1101, 7 p.Article

Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layersJANKOVIC, Nebojsa D; ARMSTRONG, G. Alastair.Microelectronics journal. 2004, Vol 35, Num 8, pp 647-653, issn 0959-8324, 7 p.Article

An analytic model for channel potential and subthreshold swing of the symmetric and asymmetric double-gate MOSFETsZHIHAO DING; GUANGXI HU; JINGLUN GU et al.Microelectronics journal. 2011, Vol 42, Num 3, pp 515-519, issn 0959-8324, 5 p.Article

Three-level stencil alignment fabrication of a high-k gate stack organic thin film transistorCVETKOVIC, Nenad V; SIDLER, Katrin; SAVU, Veronica et al.Microelectronic engineering. 2011, Vol 88, Num 8, pp 2496-2499, issn 0167-9317, 4 p.Conference Paper

Double-gate pentacene thin-film transistor with improved control in sub-threshold regionTSAMADOS, Dimitrios; CVETKOVIC, Nenad V; SIDLER, Katrin et al.Solid-state electronics. 2010, Vol 54, Num 9, pp 1003-1009, issn 0038-1101, 7 p.Conference Paper

Optimal Dual-VT Design in Sub-100-nm PD/SOI and Double-Gate TechnologiesBANSAL, Aditya; KIM, Jae-Joon; KIM, Keunwoo et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 5, pp 1161-1169, issn 0018-9383, 9 p.Article

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