A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applicationsMORISHITA, Fukashi; HAYASHI, Isamu; SHINKAWATA, Hiroki et al.IEEE International Solid-State Circuits Conference. 2004, pp 202-203, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

An 800MHz embedded DRAM with a concurrent refresh modeKIRIHATA, Toshiaki; PARRIES, Paul; WORDEMAN, Matt et al.IEEE International Solid-State Circuits Conference. 2004, pp 206-207, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Influence of bit line twisting on the faulty behavior of DRAMsAL-ARS, Zaid; HERZOG, Martin; SCHANSTRA, Ivo et al.IEEE International Workshop on Memory Technology, Design and Testing. 2004, pp 32-37, isbn 0-7695-2193-2, 1Vol, 6 p.Conference Paper

A mechanism for asymmetric data writing failureMYOUNG JIN LEE; KUN WOO PARK.Solid-state electronics. 2011, Vol 56, Num 1, pp 211-213, issn 0038-1101, 3 p.Article

A 600MHZ DSP with 24Mb embedded DRAM with an enhanced instruction set for wireless communicationADELMAN, Yehuda; AGUR, Dana; MEIROV, Henri et al.IEEE International Solid-State Circuits Conference. 2004, pp 418-419, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Radiation Hardened MRAM-Based FPGAGONCALVES, O; PRENAT, G; DIENY, B et al.IEEE transactions on magnetics. 2013, Vol 49, Num 7, pp 4355-4358, issn 0018-9464, 4 p.Conference Paper

Future prospects of DRAM: emerging alternativesCHOI, Yoonsuk; LATIFI, Shahram.International journal of high performance systems architecture (Print). 2012, Vol 4, Num 1, pp 1-12, issn 1751-6528, 12 p.Article

Challenges of long term process stability and solutions for better controlCHOI, Jinphil; SEONG, Nakgeuon; LEE, Sangho et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7272, issn 0277-786X, isbn 978-0-8194-7525-1 0-8194-7525-4, 727234.1-727234.8, 2Conference Paper

Statistical approach to design DRAM bitcell considering overlay errorsPYO, Yu-Jin; KIM, Dae-Wook; PARK, Jai-Kyun et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7275, issn 0277-786X, isbn 978-0-8194-7528-2 0-8194-7528-9, 1Vol, 72751L.1-72751L.7Conference Paper

Exploring the limits of high temperature thermal processing for advanced 8-inch power technology manufacturingRUPP, T; DYROFF, N; SORSCHAG, K et al.IEEE / SEMI advanced semiconductor manufacturing conference. 2004, pp 27-31, isbn 0-7803-8312-5, 1Vol, 5 p.Conference Paper

Application results of lot-to-lot high order overlay correction for sub-60-nm memory device fabricationSHIN, Jangho; NAM, Sangmo; KIM, Taekyu et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7272, issn 0277-786X, isbn 978-0-8194-7525-1 0-8194-7525-4, 72721R.1-72721R.5, 2Conference Paper

CD Budget Analysis on Sub-50nm DRAM Device: Global CD Variation to Local CD VariationHWANG, Chan; PARK, Joon-Soo; YEO, Jeongho et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7272, issn 0277-786X, isbn 978-0-8194-7525-1 0-8194-7525-4, 72722O.1-72722O.8, 2Conference Paper

Crosstalk induced fault analysis in DRAMsZEMO YANG; WILLIAM, Samiha Mourad; TERRY, Janice et al.IEEE Systems-on-chip conference. 2004, pp 171-172, isbn 0-7803-8445-8, 1Vol, 2 p.Conference Paper

A 2Gb/s point-to-point heterogeneous voltage capable DRAM interface for capacity-scalable memory subsystemsKENNEDY, Joseph; ELLIS, Robert; CHO, Sdo-In et al.IEEE International Solid-State Circuits Conference. 2004, pp 214-215, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Improved yield models for fault-tolerant memory chipsSTAPPER, C. H.IEEE transactions on computers. 1993, Vol 42, Num 7, pp 872-881, issn 0018-9340Article

On the design of hybrid DRAM/SRAM memory schemes for fast packet buffersGARCIA, Jorge; MARCH, Maribel; CERDA, Llorenc et al.Workshop on high performance switching and routing. 2004, pp 15-19, isbn 0-7803-8375-3, 1Vol, 5 p.Conference Paper

A 4Gb/s/pin 4-level simultaneous bidirectional 10 using a 500MHz clock for high-speed memoryKIM, Jin-Hyun; KIM, Su-A; KIM, Woo-Seop et al.IEEE International Solid-State Circuits Conference. 2004, pp 248-249, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

The effectiveness of scan test and its new variantsVAN DE GOOR, Ad J; HAMDIOUI, Said; AL-ARS, Zaid et al.IEEE International Workshop on Memory Technology, Design and Testing. 2004, pp 26-31, isbn 0-7695-2193-2, 1Vol, 6 p.Conference Paper

Resistive-Memory EmbeddedKIM, Sungho; CHOI, Sung-Jin; CHOI, Yang-Kyu et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 11, pp 2670-2674, issn 0018-9383, 5 p.Article

Characterization of the Variable Retention Time in Dynamic Random Access MemoryKIM, Heesang; OH, Byoungchan; SON, Younghwan et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 9, pp 2952-2958, issn 0018-9383, 7 p.Article

Reduction of Bipolar Disturb of Floating-Body Cell (FBC) by Silicide and Thin Silicon Film Formed at Source and Drain RegionsHAMAMOTO, Takeshi; FUKUZUMI, Yoshiaki; HIGASHI, Tomoki et al.I.E.E.E. transactions on electron devices. 2010, Vol 57, Num 8, pp 1781-1788, issn 0018-9383, 8 p.Article

Performance modeling of resonant tunneling-based random-access memoriesHUI ZHANG; MAZUMDER, Pinaki; LI DING et al.IEEE transactions on nanotechnology. 2005, Vol 4, Num 4, pp 472-480, issn 1536-125X, 9 p.Article

Extending storage dielectric scaling limit by reoxidizing nitrided NO dielectric for trench DRAMWU, Yung-Hsien; HSIEH, Eugine; KUO, Robert et al.IEEE electron device letters. 2005, Vol 26, Num 2, pp 66-68, issn 0741-3106, 3 p.Article

A Sensing Noise Compensation Bit Line Sense Amplifier for Low Voltage ApplicationsMYOUNG JIN LEE.IEEE journal of solid-state circuits. 2011, Vol 46, Num 3, pp 690-694, issn 0018-9200, 5 p.Article

Using Embedded Dynamic Random Access Memory to Reduce Energy Consumption of Magnetic Recording Read ChannelNINGDE XIE; TONG ZHANG; HARATSCH, Erich F et al.IEEE transactions on magnetics. 2010, Vol 46, Num 1, pp 87-91, issn 0018-9464, 5 p.Article