INTERCONNECTION DELAYS IN MOSFET VLSIELMASRY MI.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 5; PP. 585-591; BIBL. 8 REF.Article

LOGIC DESIGN USING EFL STRUCTURES.ELMASRY MI.1976; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1976; VOL. 25; NO 9; PP. 952-956; BIBL. 20 REF.Article

NANOSECOND NMOS VLSI CURRENT MODE LOGICELMASRY MI.1982; IEEE TRANS. ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 4; PP. 781-784; BIBL. 4 REF.Article

FOLDED-COLLECTOR INTEGRATED INJECTION LOGIC.ELMASRY MI.1976; I.E.E.E. J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1976; VOL. 11; NO 5; PP. 644-647; BIBL. 22 REF.Article

NONSATURATED INTEGRATED INJECTION LOGIC. = LOGIQUE A INJECTION INTEGREE NON SATUREEELMASRY MI.1975; ELECTRON. LETTERS; G.B.; DA. 1975; VOL. 11; NO 3; PP. 63-64; BIBL. 6 REF.Article

BIPOLAR STRUCTURES FOR BIMOS TECHNOLOGIESHAMDY EZ; ELMASRY MI.1980; I.E.E.E. J. SOLID STATE CIRCUITS; USA; DA. 1980; VOL. 15; NO 2; PP. 229-236; BIBL. 19 REF.Article

LOAD-LINE ANALYSIS OF I.I.L.ELMASRY MI; MIDHA RD.1975; ELECTRON. LETTERS; G.B.; DA. 1975; VOL. 11; NO 3; PP. 68-69; BIBL. 5 REF.Article

SDW MOSFET'S IN LSI ANALOG CIRCUIT DESIGNHAMDY EZ; ELMASRY MI.1982; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1982; VOL. 17; NO 1; PP. 2-8; BIBL. 7 REF.Article

SDW MOS FET STATIC MEMORY CELLELMASRY MI; HAMDY EZ.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 2; PP. 80-85; BIBL. 14 REF.Article

A DOL CMOS STATIC MEMORY CELLELMASRY MI; PETERSON LR.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 5; PP. 466-471; BIBL. 12 REF.Article

LOGIC PARTITION FOR MULTIEMITTER TWO-LEVEL STRUCTURES.ELMASRY MI; THOMPSON PM.1974; I.E.E.E. TRANS. CIRCUITS SYST.; U.S.A.; DA. 1974; VOL. 21; NO 3; PP. 354-359; BIBL. 12 REF.Article

BASE COMPONENT OF GAIN AND DELAY TIME IN BASE-IMPLANTED BIPOLAR TRANSISTORSELMASRY MI; ROULSTON DJ.1981; SOLID-STATE ELECTRON.; ISSN 0038-1101; GBR; DA. 1981; VOL. 24; NO 4; PP. 371-375; BIBL. 15 REF.Article

THE EFFECT OF COLLECTOR LOCATION ON BETA _U OF I²L STRUCTURES.ROFAIL SS; ELMASRY MI.1977; I.E.E.E. TRANS. ELECTRON DEVICES; U.S.A.; DA. 1977; VOL. 24; NO 3; PP. 289-291; BIBL. 7 REF.Article

FUNCTIONAL MODELLING OF NON-VOLATILE MOS MEMORY DEVICES.CARD HC; ELMASRY MI.1976; SOLID-STATE ELECTRON.; G.B.; DA. 1976; VOL. 19; NO 10; PP. 863-870; BIBL. 32 REF.Article

TWO-LEVEL EMITTER-FUNCTION LOGIC STRUCTURES FOR LOGIC-IN-MEMORY COMPUTERS.ELMASRY MI; THOMPSON PM.1975; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1975; VOL. 24; NO 3; PP. 250-258; BIBL. 17 REF.Article

SCALING MERGED SINGLE-DEVICE-WELL MOSFETS FOR VERY LARGE SCALE INTEGRATIONELSAID MH; ELMASRY MI.1981; SOLID-STATE ELECTRON.; ISSN 0038-1101; GBR; DA. 1981; VOL. 24; NO 10; PP. 967-973; BIBL. 8 REF.Article

A CMOS PIPELINED SINGLE CHANNEL DIGITAL ECHO CANCELLERMITCHLER DW; ELMASRY MI.1981; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1981; VOL. 16; NO 4; PP. 377-379; BIBL. 7 REF.Article

FUNCTIONAL MODELING OF INTEGRATED INJECTION LOGIC. TRANSIENT ANALYSISROFAIL SS; ELMASRY MI; HEASELL EL et al.1978; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1978; VOL. 25; NO 9; PP. 1120-1125; BIBL. 11 REF.Article

INTEGRATED INJECTION LOGIC FOR VLSIROFAIL SS; ELMASRY MI; HEASELL EL et al.1980; I.E.E.E. TRANS. ELECTRON DEVICES; USA; DA. 1980; VOL. 27; NO 7; PP. 1301-1303; BIBL. 8 REF.Article

WATPAC: A COMPUTER-AIDED DESIGN PACKAGE FOR DIGITAL BIPOLAR INTEGRATED CIRCUITSTEENE AR; ELMASRY MI; ROULSTON DJ et al.1982; IEEE TRANS. COMPUT.-AIDED DES. INTEGR. CIRCUITS SYST.; ISSN 50629X; USA; DA. 1982; VOL. 1; NO 4; PP. 213-219; BIBL. 12 REF.Article