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Problems in designing thin-film accumulation-mode p-channel soi MOSFETs for CMOS digital circuit environmentFLANDRE, D.Electronics Letters. 1991, Vol 27, Num 14, pp 1280-1282, issn 0013-5194Article

Extended theoretical analysis of the steady-state linear behaviour of accumulation-mode, long-channel p-MOSFETs on SOI substratesFLANDRE, D; TERAO, A.Solid-state electronics. 1992, Vol 35, Num 8, pp 1085-1092, issn 0038-1101Article

Kink-like effect in long n-channel twin-gate fully-depleted SOI MOSFETsDE CEUSTER, D; FLANDRE, D.Electronics Letters. 1994, Vol 30, Num 17, pp 1456-1458, issn 0013-5194Article

On the great potential of non-doped MOSFETs for analog applications in partially-depleted SOI CMOS processKILCHYTSKA, V; LEVACQ, D; VANCAILLIE, L et al.Solid-state electronics. 2005, Vol 49, Num 5, pp 708-715, issn 0038-1101, 8 p.Article

Unusual floating body effect in fully depleted MOSFETsBAWEDIN, M; CRISTOLOVEANU, S; FLANDRE, D et al.IEEE international SOI conference. 2004, pp 151-152, isbn 0-7803-8497-0, 1Vol, 2 p.Conference Paper

A voltage reference compatible with standard SOI CMOS processes and consuming 1pA to 50nA from room temperature up to 300°CADRIAENSEN, S; DESSARD, V; FLANDRE, D et al.IEEE International SOI conference. 2002, pp 130-131, isbn 0-7803-7439-8, 2 p.Conference Paper

LDMOS in SOI technology with very-thin silicon filmBAWEDIN, M; RENAUX, C; FLANDRE, D et al.Solid-state electronics. 2004, Vol 48, Num 12, pp 2263-2270, issn 0038-1101, 8 p.Article

Silicon-on-insulator technology for high temperature metal oxide semiconductor devices and circuitsFLANDRE, D.Materials science & engineering. B, Solid-state materials for advanced technology. 1995, Vol 29, Num 1-3, pp 7-12, issn 0921-5107Conference Paper

Comparison of self-heating effect in GAA and SOI mosfetsFRANCIS, P; COLINGE, J. P; FLANDRE, D et al.Microelectronics and reliability. 1997, Vol 37, Num 1, pp 61-75, issn 0026-2714Article

Subthreshold slope of long-channel accumulation-mode p-channel SOI MOSFETsCOLINGE, J. P; FLANDRE, D; VAN DE WIELE, F et al.Solid-state electronics. 1994, Vol 37, Num 2, pp 289-294, issn 0038-1101Article

Detector of abrupt current variations on power linesDRUART, S; GILLIS, J. M; MARTIN, N et al.Electronics letters. 2013, Vol 49, Num 14, pp 901-903, issn 0013-5194, 3 p.Article

Impact of self-heating and substrate effects on small-signal output conductance in UTBB SOI MOSFETsMAKOVEJEV, S; RASKIN, J.-P; ARSHAD, M. K. Md et al.Solid-state electronics. 2012, Vol 71, pp 93-100, issn 0038-1101, 8 p.Conference Paper

Impact of neutron irradiation on the RF properties of oxidized high-resistivity silicon substrates with and without a trap-rich passivation layerRODA NEVE, C; KILCHYTSKA, V; ALVARADO, J et al.Microelectronics and reliability. 2011, Vol 51, Num 2, pp 326-331, issn 0026-2714, 6 p.Article

NANOSIL network of excellence—silicon—based nanostructures and nanodevices for long-term nanoelectronics applicationsBALESTRA, F; PARKER, E; LEMME, M et al.Materials science in semiconductor processing. 2008, Vol 11, Num 5-6, pp 148-159, issn 1369-8001, 12 p.Conference Paper

Silicon-on-Nothing MOSFETs : An efficient solution for parasitic substrate coupling suppression in SOI devicesKILCHYTSKA, V; FLANDRE, D; RASKIN, J.-P et al.Applied surface science. 2008, Vol 254, Num 19, pp 6168-6173, issn 0169-4332, 6 p.Conference Paper

FinFET analogue characterization from DC to 110 GHzLEDERER, D; KILCHYTSKA, V; RUDENKO, T et al.Solid-state electronics. 2005, Vol 49, Num 9, pp 1488-1496, issn 0038-1101, 9 p.Article

SOI-CMOS compatible low-power gas sensor using sputtered and drop-coated metal-oxide active layersIVANOV, P; LACONTE, J; RASKIN, J. P et al.Symposium on Design, Test, Integration and Packaging of MWMS/MOEMS. 2004, pp 137-142, isbn 2-84813-026-1, 6 p.Conference Paper

Substrate effects on the small-signal characteristics of SOI MOSFETsKILCHYTSKA, V; LEVACQ, D; LEDERER, D et al.ESSCIRC 2002 : European solid-state circuits conferenceEuropean solid-state device research conference. 2002, pp 519-522, isbn 88-900847-8-2, 4 p.Conference Paper

Moderate inversion model of ultrathin double-gate nMOS/SOI transistorsFRANCIS, P; TERAO, A; FLANDRE, D et al.Solid-state electronics. 1995, Vol 38, Num 1, pp 171-176, issn 0038-1101Article

Comparison of SOI versus bulk performances of CMOS micropower single-state OTAsFLANDRE, D; EGGERMONT, J.-P; DE CEUSTER, D et al.Electronics Letters. 1994, Vol 30, Num 23, pp 1933-1934, issn 0013-5194Article

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applicationsKILCHYTSKA, V; BOL, D; DE VOS, J et al.Solid-state electronics. 2013, Vol 84, pp 28-37, issn 0038-1101, 10 p.Conference Paper

Characterization and modelling of single event transients in LDMOS-SOI FETsALVARADO, J; KILCHYTSKA, V; BOUFOUSS, E et al.Microelectronics and reliability. 2011, Vol 51, Num 9-11, pp 2004-2009, issn 0026-2714, 6 p.Conference Paper

Effect of high-energy neutrons on MuGFETsKILCHYTSKA, V; ALVARADO, J; COLLAERT, N et al.Solid-state electronics. 2010, Vol 54, Num 2, pp 196-204, issn 0038-1101, 9 p.Article

Self-cascode SOI versus graded-channel SOI MOS transistorsSANZ, M. T; CELMA, S; CALVO, B et al.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 5, pp 461-465, issn 1350-2409, 5 p.Article