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Comprehensive analysis of InGaP/GaAs heterojunction bipolar transistors (HBTs) with different thickness of setback layersCHENG, Shiou-Ying; CHEN, Chun-Yuan; CHEN, Jing-Yuh et al.SPIE proceedings series. 2004, pp 384-391, isbn 0-8194-5169-X, 8 p.Conference Paper

New metal gate architecture achieved by chemical vapor deposition for a complete tunnel fillREGNIER, C; WACQUANT, F; LEVERD, F et al.Proceedings - Electrochemical Society. 2003, pp 391-396, issn 0161-6374, isbn 1-56677-396-2, 6 p.Conference Paper

Isotropic etching of SiGe alloys with high selectivity to similar materialsBOREL, S; ARVET, C; BILDE, J et al.Microelectronic engineering. 2004, Vol 73-74, pp 301-305, issn 0167-9317, 5 p.Conference Paper

Raised S/D gate-all-around CMOS using MILCCHUNSHAN YIN; CHAN, Philip C. H; CHAN, Victor W. C et al.IEEE International SOI conference. 2002, pp 39-40, isbn 0-7803-7439-8, 2 p.Conference Paper

Minimizing variation in the electrical characteristics of gate-all-around thin film transistors through the use of multiple-channel nanowire and NH3 plasma treatmentHUANG, Po-Chun; CHEN, Lu-An; CHEN, Chen-Chia et al.Microelectronic engineering. 2012, Vol 91, pp 54-58, issn 0167-9317, 5 p.Article

Extracting Mobility Degradation and Total Series Resistance of Cylindrical Gate-All-Around Silicon Nanowire Field-Effect TransistorsCHOI, Luryi; BYOUNG HAK HONG; LEE, Won-Seong et al.IEEE electron device letters. 2009, Vol 30, Num 6, pp 665-667, issn 0741-3106, 3 p.Article

High-Performance Twin Silicon Nanowire MOSFET (TSNWFET) on Bulk Si Wafer : Nanotechnology materials and devicesSUNG DAE SUK; KYOUNG HWAN YEO; SUNG HWAN KIM et al.IEEE transactions on nanotechnology. 2008, Vol 7, Num 2, pp 181-184, issn 1536-125X, 4 p.Article

Device design guidelines for nano-scale MuGFETsLEE, Chi-Woo; YUN, Se-Re-Na; YU, Chong-Gun et al.Solid-state electronics. 2007, Vol 51, Num 3, pp 505-510, issn 0038-1101, 6 p.Article

Observation of metal-layer stress on Si nanowires in gate-all-around high-κ/metal-gate device structuresSINGH, N; FANG, W. W; RUSTAGI, S. C et al.IEEE electron device letters. 2007, Vol 28, Num 7, pp 558-561, issn 0741-3106, 4 p.Article

Impact of compositionally graded base regions on the DC and RF properties of reduced turn-on voltage InGaP-GaInAsN DHBTsSTEVENS, Kevin S; WELTY, Rebecca J; WELSER, Roger E et al.I.E.E.E. transactions on electron devices. 2004, Vol 51, Num 10, pp 1545-1553, issn 0018-9383, 9 p.Article

Analytical Quantum-Confinement Model for Short-Channel Gate-All-Around MOSFETs Under Subthreshold RegionWU, Yu-Sheng; PIN SU.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 11, pp 2720-2725, issn 0018-9383, 6 p.Article

Gate-all-around MOSFETs : lateral ultra-narrow (≤10nm) fin as channel bodySINGH, N; AGARWAL, A; BERA, L. K et al.Electronics Letters. 2005, Vol 41, Num 24, pp 1353-1354, issn 0013-5194, 2 p.Article

Impact of the graded-channel architecture on double gate transistors for high-performance analog applicationsPAVANELLO, M. A; MARTINO, J. A; CHUNG, T. M et al.Proceedings - Electrochemical Society. 2003, pp 261-266, issn 0161-6374, isbn 1-56677-375-X, 6 p.Conference Paper

Corner Effect and Local Volume Inversion in SiNW FETsDE MICHIELIS, Luca; EMILIE MOSELUND, Kirsten; SELMI, Luca et al.IEEE transactions on nanotechnology. 2011, Vol 10, Num 4, pp 810-816, issn 1536-125X, 7 p.Article

Hole Mobility Characteristics in Si Nanowire pMOSFETs on (110) Silicon-on-InsulatorJIEZHI CHEN; SARAYA, Takuya; HIRAMOTO, Toshiro et al.IEEE electron device letters. 2010, Vol 31, Num 11, pp 1181-1183, issn 0741-3106, 3 p.Article

Numerical analysis of Double Gate and Gate All Around MOSFETs with bulk trap statesABDI, M. A; DJEFFAL, F; ARAR, D et al.Journal of materials science. Materials in electronics. 2008, Vol 19, issn 0957-4522, S248-S253, SUP1Conference Paper

High threshold voltage matching performance on gate-all-around MOSFETCATHIGNOL, Augustin; CROS, Antoine; HARRISON, Samuel et al.Solid-state electronics. 2007, Vol 51, Num 11-12, pp 1450-1457, issn 0038-1101, 8 p.Conference Paper

Multiple gate devices : advantages and challengesPOIROUX, T; VINET, M; FAYNOT, O et al.Microelectronic engineering. 2005, Vol 80, pp 378-385, issn 0167-9317, 8 p.Conference Paper

50nm: Gate all around (GAA): Silicon on nothing (SON): Devices: A simple way to co-integration of GAA transistors within bulk MOSFET processMONFRAY, S; SKOTNICKI, T; HAOND, M et al.Symposium on VLSI technology. 2002, pp 108-109, isbn 0-7803-7312-X, 2 p.Conference Paper

Junctionless Vertical-Si-Nanowire-Channel-Based SONOS Memory With 2-Bit Storage per CellSUN, Y; YU, H. Y; SINGH, N et al.IEEE electron device letters. 2011, Vol 32, Num 6, pp 725-727, issn 0741-3106, 3 p.Article

Modeling Short-Channel Effect of Elliptical Gate-All-Around MOSFET bv Effective RadiusLINING ZHANG; LIN LI; JIN HE et al.IEEE electron device letters. 2011, Vol 32, Num 9, pp 1188-1190, issn 0741-3106, 3 p.Article

Uniaxial Strain Effects on Electron Ballistic Transport in Gate-All-Around Silicon Nanowire MOSFETsLINING ZHANG; HAIJUN LOU; JIN HE et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 11, pp 3829-3836, issn 0018-9383, 8 p.Article

Impact of Gate Electrodes on 1/f Noise of Gate-All-Around Silicon Nanowire TransistorsCHENGQING WEI; YU JIANG; XIONG, Yong-Zhong et al.IEEE electron device letters. 2009, Vol 30, Num 10, pp 1081-1083, issn 0741-3106, 3 p.Article

Design optimization of gate-all-around (GAA) MOSFETsJAE YOUNG SONG; WOO YOUNG CHOI; JU HEE PARK et al.IEEE transactions on nanotechnology. 2006, Vol 5, Num 3, pp 186-191, issn 1536-125X, 6 p.Conference Paper

Universality of Short-Channel Effects in Undoped-Body Silicon Nanowire MOSFETsBANGSARUNTIP, Sarunya; COHEN, Guy M; MAJUMDAR, Amlan et al.IEEE electron device letters. 2010, Vol 31, Num 9, pp 903-905, issn 0741-3106, 3 p.Article

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