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Careful examination on the asymmetric Vfb shift problem for poly-Si/HfSiON gate stack and its solution by the Hf concentration control in the dielectric near the poly-Si interface with small EOT expenseKOYAMA, Masato; KAMIMUTA, Yuuichi; INO, Tsunehiro et al.International Electron Devices Meeting. 2004, pp 499-502, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Self-aligned GaAs MISFET's with a low-temperature-grown GaAs gate insulatorCHEN, C. L; MAHONEY, L. J; NICHOLS, K. B et al.IEEE electron device letters. 1995, Vol 16, Num 5, pp 199-201, issn 0741-3106Article

Modeling and characterization of gate oxide reliabilityLEE, J. C; IH-CHIN CHEN; CHENMING HU et al.I.E.E.E. transactions on electron devices. 1988, Vol 35, Num 12, pp 2268-2278, issn 0018-9383Article

Structure of the breakdown spot during progressive breakdown of ultra-thin gate oxidesPALUMBO, F; LOMBARDO, S; PEY, K. L et al.IEEE international reliability physics symposium. 2004, pp 583-584, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper

Thin polyoxide on the top of poly-Si gate to suppress boron penetration for pMOSYUNG HAO LIN; CHUNG CHEN LEE; TAN FU LEI et al.IEEE electron device letters. 1995, Vol 16, Num 5, pp 164-165, issn 0741-3106Article

Characterization of metal-oxide-semiconductor transistors with very thin gate oxideHUNG, K. K; CHENG, Y. C.Journal of applied physics. 1986, Vol 59, Num 3, pp 816-823, issn 0021-8979Article

The role of surface-gate technology for AlGaAs/GaAs nanostructuresTAYLOR, R. P.Nanotechnology (Bristol. Print). 1994, Vol 5, Num 4, pp 183-198, issn 0957-4484Article

Evaluation of phase-edge phase-shifting mask for sub-0.18 μm gate patterns in logic devicesCHA, D.-H; KYE, J.-W; SEONG, N.-G et al.SPIE proceedings series. 1998, pp 46-54, isbn 0-8194-2779-9Conference Paper

New method for lifetime evaluation of gate oxide damaged by plasma processingERIGUCHI, K; URAOKA, Y.IEEE electron device letters. 1995, Vol 16, Num 5, pp 187-189, issn 0741-3106Article

Implanted-silicided polysilicon gates for VLSI transistorsPETERS, D.I.E.E.E. transactions on electron devices. 1986, Vol 33, Num 9, pp 1391-1393, issn 0018-9383Article

Ga0.47In0.53As field-effect transistors with a lattice-mismatched reduced leakage current GaAs gateGARBINSKI, P. A; CHEN, C. Y; CHO, A. Y et al.Electronics Letters. 1986, Vol 22, Num 5, pp 236-238, issn 0013-5194Article

The electrical properties of subquarter-micrometer gate-length MOSFET'sHAN-SHENG LEE; CHERYL PUZIO, L.IEEE electron device letters. 1986, Vol 7, Num 11, pp 612-614, issn 0741-3106Article

A novel gate-suppression technique for ESD protectionMENG MIAO; SHURONG DONG; MINGLIANG LI et al.Microelectronics and reliability. 2012, Vol 52, Num 8, pp 1598-1601, issn 0026-2714, 4 p.Conference Paper

Subnanometer-precision metrology for 100nm gate linewidth controlMONAHAN, K. M; MACNAUGHTON, C; NG, W et al.SPIE proceedings series. 1998, pp 110-123, isbn 0-8194-2777-2Conference Paper

Low-temperature processed MOSFET's with liquid phase deposited SiO2-xFx as gate insulatorCHING-FA YEH; SHYUE-SHYH LIN; TZY-YAN HONG et al.IEEE electron device letters. 1995, Vol 16, Num 7, pp 316-318, issn 0741-3106Article

Gate technology for 89 GHz vertical doping engineered Si metal-oxide semiconductor field effect transistorJEON, D. Y; TENNANT, D. M; KIM, Y. O et al.Journal of vacuum science & technology. B. Microelectronics and nanometer structures. Processing, measurement and phenomena. 1992, Vol 10, Num 6, pp 2922-2926, issn 1071-1023Conference Paper

Platinum-platinum oxide gate pH ISFETTSUKADA, K; MIYAHARA, Y; MIYAGI, H et al.Japanese journal of applied physics. 1989, Vol 28, Num 12, pp 2450-2453, issn 0021-4922, 1Article

GATE FLICKER NOISE IN MOSFET'SHASLETT JW; KENDALL EJM.1972; PROC. I.E.E.E.; U.S.A.; DA. 1972; VOL. 60; NO 9; PP. 1111-1112; BIBL. 3 REF.Serial Issue

Gate dielectric breakdown : A focus on ESD protectionWEIR, Bonnie E; LEUNG, Che-Choi; SILVERMAN, Paul J et al.IEEE international reliability physics symposium. 2004, pp 399-404, isbn 0-7803-8315-X, 1Vol, 6 p.Conference Paper

0.18 μm optical lithography performances using an alternating DUV phase shift maskTROUILLER, Y; BUFFET, N; MOURIER, T et al.SPIE proceedings series. 1998, pp 25-35, isbn 0-8194-2779-9Conference Paper

A novel method to characterize MOS transistors with mixed gate dielectric technologiesSIERGIEJ, R. R; WHITE, M. H.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 734-737, issn 0018-9383Article

Advanced gate stack, source/drain and channel engineering for Si-based CMOS : naw materials, processes, and equipment (Quebec PQ, 16-18 May 2005)Gusev, Evgeni P; Iwai, Hiroshi; Öztürk, Mehmet C et al.Proceedings - Electrochemical Society. 2005, issn 0161-6374, isbn 1-56677-463-2, XV, 634 p, isbn 1-56677-463-2Conference Proceedings

Line edge roughness: Characterization, modeling and impact on device behaviorCROON, J. A; STORMS, G; WINKELMEIER, S et al.IEDm : international electron devices meeting. 2002, pp 307-310, isbn 0-7803-7462-2, 4 p.Conference Paper

Effect of n+―polycrystalline silicon gate rapid thermal annealing on the electrical properties of the gate oxideKOREC, J; STEFFEN, A; MCGINTY, G. K et al.Thin solid films. 1988, Vol 162, pp 21-28, issn 0040-6090Article

Transistor action in novel GaAs/W/GaAs structuresDERKITS, G. E. JR; HARBISON, J. P; LEVKOFF, J et al.Applied physics letters. 1986, Vol 48, Num 18, pp 1220-1222, issn 0003-6951Article

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