A fast nonenumerative automatic test pattern generator for path delay faultsTRAGOUDAS, S; KARAYIANNIS, D.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 7, pp 1050-1057, issn 0278-0070Article

A methodology for concurrent process-circuit optimizationLOKANATHAN, A. N; BROCKMAN, J. B.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 7, pp 889-902, issn 0278-0070Article

Accurate high-speed performance prediction for full differential current-mode logic : The effect of dielectric anisotropyGARG, A; LE COZ, Y. L; CARLOUGH, S. R et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 212-219, issn 0278-0070Article

Analog testing by characteristic observation inferenceLINDERMEIR, W. M; GRAEB, H. E; ANTREICH, K. J et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 9, pp 1353-1368, issn 0278-0070Article

Combining multiple DFT schemes with test generationMATHEW, B; SAAB, D. G.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 6, pp 685-696, issn 0278-0070Article

Configuration compression for the Xilinx XC6200 FPGAHAUCK, S; ZHIYUANLI; SCHWABE, E et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 8, pp 1107-1113, issn 0278-0070Article

Diagnosis of clustered faults for identical degree topologiesTANG, Q.-Y; XIAOYU SONG; YUKE WANG et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 8, pp 1192-1201, issn 0278-0070Article

Evaluation and optimization of replication algorithms for logic bipartitioningENOS, M; HAUCK, S; SARRAFZADEH, M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 9, pp 1237-1248, issn 0278-0070Article

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxationCHEN, C.-P; CHU, C. C. N; WONG, D. F et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 7, pp 1014-1025, issn 0278-0070Article

GLFSR : A new test pattern generator for built-in-self-testPRADHAN, D. K; CHATTERJEE, M.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 239-247, issn 0278-0070Article

High-level synthesis of power-optimized and area-optimized circuits from hierarchical data-flow intensive behaviorsLAKSHMINARAYANA, G; JHA, N. K.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 3, pp 265-281, issn 0278-0070Article

Methodology for electromigration critical threshold design rule evaluationCLEMENT, J. J; RIEGE, S. P; CVIJETIC, R et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 5, pp 576-581, issn 0278-0070Article

Models and algorithms for bounds on leakage in CMOS circuitsJOHNSON, M. C; SOMASEKHAR, D; ROY, K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 6, pp 714-725, issn 0278-0070Article

On the design of optimal counter-based schemes for test set embeddingKAGARIS, D; TRAGOUDAS, S.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 219-230, issn 0278-0070Article

On wirelength estimations for row-based placementCALDWELL, A. E; KAHNG, A. B; MANTIK, S et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 9, pp 1265-1278, issn 0278-0070Article

Register transfer level power optimization with emphasis on glitch analysis and reductionRAGHUNATHAN, A; DEY, S; JHA, N. K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 8, pp 1114-1131, issn 0278-0070Article

Substrate optimization based on semi-analytical techniquesCHARBON, E; GHARPUREY, R; MEYER, R. G et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 172-190, issn 0278-0070Article

Using configurable computing to accelerate Boolean satisfiabilityPEIXIN ZHONG; MARTONOSI, M; ASHAR, P et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 6, pp 861-868, issn 0278-0070Article

Critical area computation via Voronoi diagramsPAPADOPOULOU, E; LEE, D. T.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 4, pp 463-474, issn 0278-0070Conference Paper

Physical designSARRAFZADEH, Majid; WONG, Martin D. F.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 4, issn 0278-0070, 129 p.Conference Proceedings

An improved method for computing a generalized spectral coefficientMILLER, D. M.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 3, pp 233-238, issn 0278-0070Article

Automatic configuration of embedded multicomputer systemsBECK, J. E; SIEWIOREK, D. P.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 2, pp 84-95, issn 0278-0070Article

Covering conditions and algorithms for the synthesis of speed-independent circuitsBEEREL, P. A; MYERS, C. J; MENG, T. H et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 3, pp 205-219, issn 0278-0070Article

Diagnosing realistic bridging faults with single stuck-at informationLAVO, D. B; CHESS, B; LARRABEE, T. SR et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 3, pp 255-268, issn 0278-0070Article

Direct mapping of RTL structures onto LUT-based FPGA'sNASEER, A. R; BALAKRISHNAN, M; KUMAR, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 7, pp 624-631, issn 0278-0070Article