An easy-to-use approach for practical bus-based system designCHEN, C.-H; LIN, F.-F.IEEE transactions on computers. 1999, Vol 48, Num 8, pp 780-793, issn 0018-9340Article

A high-speed reduced-size adder under left-to-right input arrivalTAKAGI, N; HORIYAMA, T.IEEE transactions on computers. 1999, Vol 48, Num 1, pp 76-80, issn 0018-9340Article

A look-up scheme for scaling in the RNSGARCIA, A; LLORIS, A.IEEE transactions on computers. 1999, Vol 48, Num 7, pp 748-751, issn 0018-9340Article

A software cost model with warranty and risk costsHOANG PHAM; XUEMEI ZHANG.IEEE transactions on computers. 1999, Vol 48, Num 1, pp 71-75, issn 0018-9340Article

Comprehensive hardware and software support for operating systems to exploit MP memory hierarchiesCHUN XIA; TORRELLAS, J.IEEE transactions on computers. 1999, Vol 48, Num 5, pp 494-505, issn 0018-9340Article

Configuration of locally spared arrays in the presence of multiple Fault typesLAFORGE, L. E.IEEE transactions on computers. 1999, Vol 48, Num 4, pp 398-416, issn 0018-9340Article

Fast converter for 3 moduli RNS using new property of CRTCONWAY, R; NELSON, J.IEEE transactions on computers. 1999, Vol 48, Num 8, pp 852-860, issn 0018-9340Article

Parallel multiplication using fast sorting networksFIORE, P. D.IEEE transactions on computers. 1999, Vol 48, Num 6, pp 640-645, issn 0018-9340Article

Temporal partitioning and scheduling data flow graphs for reconfigurable computers : Special section on configurable computingGAJJALA PURNA, K. M; BHATIA, D.IEEE transactions on computers. 1999, Vol 48, Num 6, pp 579-590, issn 0018-9340Article

Wide-sense nonblocking Clos networks under packing strategyYUANYUAN YANG; JIANCHAO WANG.IEEE transactions on computers. 1999, Vol 48, Num 3, pp 265-284, issn 0018-9340Article

Coherence controller architectures for scalable shared-memory multiprocessorsMICHAEL, M. M; NANDA, A. K; LIM, B.-H et al.IEEE transactions on computers. 1999, Vol 48, Num 2, pp 245-255, issn 0018-9340Article

Analysis of temporal-based program behavior for improved instruction cache performanceKALAMATIANOS, J; KHALAFI, A; KAELI, D. R et al.IEEE transactions on computers. 1999, Vol 48, Num 2, pp 168-175, issn 0018-9340Article

The impact of exploiting instruction-level parallelism on shared-memory multiprocessorsPAI, V. S; RANGANATHAN, P; ABDEL-SHAFI, H et al.IEEE transactions on computers. 1999, Vol 48, Num 2, pp 218-226, issn 0018-9340Article

A mechanically checked proof of the AMD5_K86 floating-point division programMOORE, J. S; LYNCH, T. W; KAUFMANN, M et al.IEEE transactions on computers. 1998, Vol 47, Num 9, pp 913-926, issn 0018-9340Article

A reliable fail-safe systemLUBASZEWSKI, M; COURTOIS, B.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 236-241, issn 0018-9340Article

Algorithms for variable length subnet address assignmentATALLAH, M. J; COMER, D. E.IEEE transactions on computers. 1998, Vol 47, Num 6, pp 693-699, issn 0018-9340Article

Design of a high-speed square generatorWEY, C.-L; SHIEH, M.-D.IEEE transactions on computers. 1998, Vol 47, Num 9, pp 1021-1026, issn 0018-9340Article

Floating steiner treesSARRAFZADEH, M; LIN, W.-L; WONG, C. K et al.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 197-211, issn 0018-9340Article

Minimum achievable utilization for fault-tolerant processing of periodic tasksPANDYA, M; MALEK, M.IEEE transactions on computers. 1998, Vol 47, Num 10, pp 1102-1112, issn 0018-9340Article

New Svoboda-Tung divisionMONTALVO, L. A; PARTHI, K. K; GUYOT, A et al.IEEE transactions on computers. 1998, Vol 47, Num 9, pp 1014-1020, issn 0018-9340Article

Optimal circuits for parallel multipliersSTELLING, P. F; MARTEL, C. U; OKLOBDZIJA, V. G et al.IEEE transactions on computers. 1998, Vol 47, Num 3, pp 273-285, issn 0018-9340Article

Optimal diagnosis of heterogeneous systems with random faultsPELC, A.IEEE transactions on computers. 1998, Vol 47, Num 3, pp 298-304, issn 0018-9340Article

Processor saving scheduling policies for multiprocessor systemsROSTI, E; SMIRNI, E; DOWDY, L. W et al.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 178-189, issn 0018-9340Article

Random pattern testability of memory control logicSAVIR, J.IEEE transactions on computers. 1998, Vol 47, Num 3, pp 305-312, issn 0018-9340Article

Solving Boolean equations using ROSOP formsYUKE WANG; MCCROSKY, C.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 171-177, issn 0018-9340Article