Built-in self test design of power switch with clock-gated charge/discharge transistorCHEN XIN; WU NING; BAI NA et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 2, pp 59-69, issn 1751-8601, 11 p.Article

High-throughput dilution engine for sample preparation on digital microfluidic biochipsROY, Sudip; BHATTACHARYA, Bhargab B; GHOSHAL, Sarmishtha et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 4, pp 163-171, issn 1751-8601, 9 p.Article

Intensive computing on a large data volume with a short-vector single instruction multiple data processorUNGUREAN, Ioan; GAITAN, Vasile-Gheorghita; GAITAN, Nicoleta-Cristina et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 5, pp 219-228, issn 1751-8601, 10 p.Article

Physical-aware systematic multiple defect diagnosisCHEN, Po-Juei; CHE, Chieh-Chih; LI, James C.-M et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 5, pp 199-209, issn 1751-8601, 11 p.Article

eXtended Torus routing algorithm for networks-on- chip: a routing algorithm for dynamically reconfigurable networks-on-chipARASH FARHADI BELDACHI; HOLLIS, Simon; NUNEZ-YANEZ, Jose L et al.IET computers & digital techniques (Print). 2014, Vol 8, Num 3, pp 148-162, issn 1751-8601, 15 p.Article

Power domain management interface: flexible protocol interface for transaction-level power domain managementMBAREK, Ons; PEGATOQUET, Alain; AUGUIN, Michel et al.IET computers & digital techniques (Print). 2013, Vol 7, Num 4, pp 155-166, issn 1751-8601, 12 p.Article

Single-configuration fault detection in application-dependent testing of field programmable gate array interconnectsTHULASIRAMAN NANDHA KUMAR; ALMURIB, Haider Abbas F; LOMBARDI, Fabrizio et al.IET computers & digital techniques (Print). 2013, Vol 7, Num 3, pp 132-141, issn 1751-8601, 10 p.Article

Three-factor control protocol based on elliptic curve cryptosystem for universal serial bus mass storage devicesLEE, Cheng-Chi; CHEN, Chi-Tung; WU, Ping-Hsien et al.IET computers & digital techniques (Print). 2013, Vol 7, Num 1, pp 48-55, issn 1751-8601, 8 p.Article

On the trade-off of mixing scientific applications on capacity high-performance computing systemsJOKANOVIC, Ana; CARLOS SANCHO, Jose; RODRIGUEZ, German et al.IET computers & digital techniques (Print). 2013, Vol 7, Num 2, pp 81-92, issn 1751-8601, 12 p.Article

Design and evaluation of variable stages pipeline processor with low-energy techniquesNAKABAYASHI, T; SASAKI, T; OHNO, K et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 1, pp 43-49, issn 1751-8601, 7 p.Article

Efficient post-configuration testing of an asynchronous nanowire crossbar system for reliabilityLEE, J.-S; VENKATESWARAN, S; CHOI, M et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 4, pp 214-222, issn 1751-8601, 9 p.Article

Evaluation of testability enhancement using software prototypeBAREISA, E; JUSAS, V; MOTIEJUNAS, K et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 3, pp 166-172, issn 1751-8601, 7 p.Article

Exploring branch target buffer access filtering for low-energy and high-performance microarchitecturesWANG, S; HU, J; ZIAVRAS, S. G et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 1, pp 50-58, issn 1751-8601, 9 p.Article

Machine learning predictive modelling high-level synthesis design space explorationCARRION, B; WAKABAYASHI, Schafer K.IET computers & digital techniques (Print). 2012, Vol 6, Num 3, pp 153-159, issn 1751-8601, 7 p.Article

Reset and partial-reset-based functional broadside testsPOMERANZ, I; REDDY, S. M.IET computers & digital techniques (Print). 2012, Vol 6, Num 4, pp 232-239, issn 1751-8601, 8 p.Article

Behavioural synthesis utilising recursive definitionsBROWN, A. D; MILTON, D. J. D; RUSHTON, A. J et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 6, pp 362-369, issn 1751-8601, 8 p.Article

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arraysHUR, J. Y; GOOSSENS, K; MHAMDI, L et al.IET computers & digital techniques (Print). 2012, Vol 6, Num 6, pp 396-405, issn 1751-8601, 10 p.Article

Variable ordering for shared binary decision diagrams targeting node count and path length optimisation using particle swarm techniqueMITRA, A; CHATTOPADHYAY, S.IET computers & digital techniques (Print). 2012, Vol 6, Num 6, pp 353-361, issn 1751-8601, 9 p.Article

Fault tolerance for nanotechnology devices at the bit and module levels with history index of correct computationDOTAN, Y; LEVISON, N; LILJA, D et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 4, pp 221-230, issn 1751-8601, 10 p.Article

Multi-standard reconfigurable motion estimation processor for hybrid video codecsNUNEZ-YANEZ, J. L; SPITERI, T; VAFIADIS, G et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 2, pp 73-85, issn 1751-8601, 13 p.Article

Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generationPOMERANZ, I; REDDY, S. M.IET computers & digital techniques (Print). 2011, Vol 5, Num 5, pp 415-423, issn 1751-8601, 9 p.Article

Reordering the assembly instructions in basic blocks to reduce switching activities on the instruction busCHABINI, N; WOLF, M. C.IET computers & digital techniques (Print). 2011, Vol 5, Num 5, pp 386-392, issn 1751-8601, 7 p.Article

Towards virtual memory support in real-time and memory-constrained embedded applications: the interval page tableZHOU, X; PETROV, P.IET computers & digital techniques (Print). 2011, Vol 5, Num 4, pp 287-295, issn 1751-8601, 9 p.Article

Three-dimensional Integrated Circuits DesignYUAN XIE; MARCHAL, Pol.IET computers & digital techniques (Print). 2011, Vol 5, Num 3, issn 1751-8601, 63 p.Serial Issue

Routing of asynchronous Clos networksSONG, W; EDWARDS, D; LIU, Z et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 6, pp 452-467, issn 1751-8601, 16 p.Article