An efficient and optimal algorithm for simultaneous buffer and wire sizingCHU, C. C. N; WONG, D. F.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 9, pp 1297-1304, issn 0278-0070Article

An improved optimal algorithm for bubble-sorting-based non-Manhattan channel routingYAN, J.-T.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 163-171, issn 0278-0070Article

Automatic synthesis of extended burst-mode circuits : Part I (specification and hazard-free implementations)YUN, K. Y; DILL, D. L.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 101-117, issn 0278-0070Article

BDD minimization using symmetriesSCHOLL, C; MÖLLER, D; MOLITOR, P et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 81-100, issn 0278-0070Article

Equivalence checking of combinational circuits using Boolean expression diagramsHULGAARD, H; WILLIAMS, P. F; ANDERSEN, H. R et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 7, pp 903-917, issn 0278-0070Article

Equivalent circuit model of resistive IC sensors derived with the box integration methodMAIER, C; EMMENEGGER, M; TASCHINI, S et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 7, pp 1000-1013, issn 0278-0070Article

Hierarchical finite state machines with multiple concurrency modelsGIRAULT, A; BILUNG LEE; LEE, E. A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 6, pp 742-760, issn 0278-0070Article

Highly accurate and simple models for CML and ECL gatesALIOTO, M; PALUMBO, G.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 9, pp 1369-1375, issn 0278-0070Article

Resolving unknown inputs in mixed-level simulation with sequential elementsMEYASSED, M; KLENKE, R. H; AYLOR, J. H et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 8, pp 1151-1164, issn 0278-0070Article

Scan-based BIST fault diagnosisYUEJIAN WU; ADHAM, S. M. I.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 2, pp 203-211, issn 0278-0070Article

Slicing floorplans with boundary constraintsYOUNG, F. Y; WONG, D. F; YANG, H. H et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 9, pp 1385-1389, issn 0278-0070Article

Static test compaction for synchronous sequential circuits based on vector restorationPOMERANZ, I; REDDY, S. M; RUIFENG GUO et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 7, pp 1040-1049, issn 0278-0070Article

Timing verification of sequential dynamic circuitsVAN CAMPENHOUT, D; MUDGE, T; SAKALLAH, K. A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 5, pp 645-658, issn 0278-0070Article

Synthesizing controllers from real-time specificationsDIERKS, H.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 1, pp 33-43, issn 0278-0070Conference Paper

Techniques for minimizing and balancing I/O during functional partitioningVAHID, F.IEEE transactions on computer-aided design of integrated circuits and systems. 1999, Vol 18, Num 1, pp 69-75, issn 0278-0070Conference Paper

Application of genetically engineered finite-state-machine sequences to sequential circuit ATPGHSIAO, M. S; RUDNICK, E. M; PATEL, J. H et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 3, pp 239-254, issn 0278-0070Article

BDD-based synthesis of extended burst-mode controllersYUN, K. Y; LIN, B; DILL, D. L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 9, pp 782-792, issn 0278-0070Article

Four-bend top-down global routingCHO, J. D; SARRAFZADEH, D. M.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 9, pp 793-802, issn 0278-0070Article

Hardware-optimal test register insertionSTROELE, A. P; WUNDERLICH, H.-J.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 6, pp 531-539, issn 0278-0070Article

Hazard-free implementation of speed-independent circuitsKONDRATYEV, A; KISHINEVSKY, M; YAKOVLEV, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 9, pp 749-771, issn 0278-0070Article

ILLIADS-T: An electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chipsCHENG, Y.-K; RAHA, P; TENG, C.-C et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 8, pp 668-681, issn 0278-0070Article

Machine learning-based VLSI cells shape function estimationXIAO QUAN LI; MARWAN ANWAR JABRI.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 7, pp 613-623, issn 0278-0070Article

Maple-opt : A performance-oriented simultaneous technology mapping, placement, and global routing algorithm for FPGA'sTOGAWA, N; YANAGISAWA, M; OHTSUKI, T et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 9, pp 803-818, issn 0278-0070Article

Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuitsNIKNEJAD, A. M; GHARPUREY, R; MEYER, R. G et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 4, pp 305-315, issn 0278-0070Article

Telescopic units : A new paradigm for performance optimization of VLSI designsBENINI, L; MACII, E; PONCINO, M et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 3, pp 220-232, issn 0278-0070Article