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Results 1 to 25 of 1399

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Balancing electrical and optical interconnection resources at low levelsDRABIK, T. J.SPIE proceedings series. 1998, pp 556-559, isbn 0-8194-2949-XConference Paper

A fast, single-layer, area router for semi-custom analogue circuitsBUSET, O; DECLERCQ, M; FOUAD RAHALI et al.International journal of circuit theory and applications. 1992, Vol 20, Num 3, pp 283-298, issn 0098-9886Article

On the acceleration of flow-oriented circuit clusteringCHING-WEI YEH.IEEE transactions on computer-aided design of integrated circuits and systems. 1995, Vol 14, Num 10, pp 1305-1308, issn 0278-0070Article

The Corsharp Printer―Design conceptMOSELY, J.SMPTE journal (1976). 1992, Vol 101, Num 9, pp 618-621, issn 0036-1682Conference Paper

Standards for keyboard layout―the origins and scope of ISO/IEC 9995PATERSON, B.ICL technical journal. 1992, Vol 8, Num 2, pp 316-331, issn 0142-1557Article

Transforming IC layout description from the unrestricted to A restricted formatJANKOVIC, D; MILENOVIC, D; STAMENKOVIC, Z et al.International conference on microelectronic. 1997, pp 733-735, isbn 0-7803-3664-X, 2VolConference Paper

On internal-external layoutsTOLLIS, I. G.IEEE transactions on circuits and systems. 1989, Vol 36, Num 1, pp 154-156, issn 0098-4094, 3 p.Article

Sélection des fondations de ponts pour s'accorder aux conditions géologiques et topographiquesOSHIMA, K.Tsuchi to kiso. 1986, Vol 34, Num 9, pp 9-12, issn 0041-3798Article

The marey graph animation tool demoFRIEDRICH, Carsten; EADES, Peter.Lecture notes in computer science. 2001, pp 396-406, issn 0302-9743, isbn 3-540-41554-8Conference Paper

Removing edge-node intersections in drawings of graphsWEI LAI; EADES, Peter.Information processing letters. 2002, Vol 81, Num 2, pp 105-110, issn 0020-0190Article

TILT, a technology independent layout toolRIEM-VIS, R; MALIKI, G; PELLANDINI, F et al.AGEN-Mitteilungen. 1992, Num 55, pp 29-38, issn 1016-1554Conference Paper

A fast layout algorithm for k-level graphsBUCHHEIM, Christoph; JÜNGER, Michael; LEIPERT, Sebastian et al.Lecture notes in computer science. 2001, pp 229-240, issn 0302-9743, isbn 3-540-41554-8Conference Paper

Analyse du couplage dans des interconnexions multicouches avec des plans de masse grillagés = Coupling analysis in multilayer interconnections with grided layout plansGOLOVANOV, C; NDAGIJIMANA, F.Journées nationales microondes. 1997, pp 310-311, 2VolConference Paper

Design assistant approach to analogue layout generationBENSOUIAH, D. A; MACK, R. J; MASSARA, R. E et al.IEE proceedings. Circuits, devices and systems. 1996, Vol 143, Num 4, pp 213-217, issn 1350-2409Article

Dual conformance index-based robotic arm placement and adaptationCLOUTIER, G. M; GOURDEAU, R; ST-ARNEAULT, C et al.Journal of robotic systems. 1996, Vol 13, Num 4, pp 187-202, issn 0741-2223Article

Note on opticam tile partition for space region of integrated-circuit geometryKU, L.-P; LEONG, H. W.IEE proceedings. Computers and digital techniques. 1996, Vol 143, Num 4, pp 246-248, issn 1350-2387Article

Technology description methods for LIGA processesBRÜCK, R; HAHN, K; STIENECKER, J et al.Journal of micromechanics and microengineering (Print). 1995, Vol 5, Num 2, pp 196-198, issn 0960-1317Conference Paper

A new method to compute registration error from DFM type test structuresKUNDU, N. N; RAHMAN, M. A.IEEE transactions on semiconductor manufacturing. 1992, Vol 5, Num 2, pp 163-165, issn 0894-6507Article

Finding building shapes that minimize mean trip times = Trouver des formes de bâtiments pour optimiser les temps moyens de déplacementJOHNSON, R. V.Computer-aided design. 1992, Vol 24, Num 2, pp 105-113, issn 0010-4485Article

A small pixed CMD image sensorOGATA, M; NAKAMURA, T; MATSUMOTO, K et al.I.E.E.E. transactions on electron devices. 1991, Vol 38, Num 5, pp 1005-1010, issn 0018-9383Article

Analogue implementation of the Hough transformBEN-TZVI, D; SANDLER, M.IEE proceedings. Part G. Circuits devices and systems. 1991, Vol 138, Num 4, pp 457-462, issn 0956-3768Article

Dot matrix display system for Korean numeralsGOH, W. L; LAU, K. T.IEEE transactions on consumer electronics. 1991, Vol 37, Num 4, pp 892-896, issn 0098-3063Article

Numerical test for semidefiniteness of functional matricesBAJIC, V. B.IEEE transactions on circuits and systems. 1990, Vol 37, Num 5, pp 642-644, issn 0098-4094Article

Graph layout for displaying data structuresWADDLE, Vance.Lecture notes in computer science. 2001, pp 241-252, issn 0302-9743, isbn 3-540-41554-8Conference Paper

Cell-based layout techniques supporting gate-level voltage scaling for low powerYEH, Chingwei; KANG, Yin-Shuin.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 5, pp 629-633, issn 1063-8210Conference Paper

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