Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("Implantation circuit intégré")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 351

  • Page / 15
Export

Selection :

  • and

A new transistor folding algorithm applied to an automatic full-custom layout generation toolBASTIAN, Fabricio B; LAZZARI, Cristiano; GUNTZEL, Jose Luis et al.Lecture notes in computer science. 2004, pp 732-741, issn 0302-9743, isbn 3-540-23095-5, 10 p.Conference Paper

Inspection of aggressive OPC using aerial image-based mask inspectionHSU, Luke T. H; HUNG, Johnson C. C; HSIEH, H. C et al.SPIE proceedings series. 2003, pp 357-363, isbn 0-8194-4996-2, 7 p.Conference Paper

Non-Uniform Yield Optimization for Integrated Circuit Layout Considering Global InteractionsANDRES TORRES, J; PIKUS, Fedor G.Proceedings of SPIE, the International Society for Optical Engineering. 2008, Vol 7122, issn 0277-786X, isbn 978-0-8194-7355-4 0-8194-7355-3, 71223R.1-71223R.8, 2Conference Paper

Hexagonal three-layer channel routingXUEHOU TAN; XIAOYU SONG.Information processing letters. 1995, Vol 55, Num 4, pp 223-228, issn 0020-0190Article

Generating random benchmark circuits for floorplanningTAO WAN; CHRZANOWSKA-JESKE, Malgorzata.IEEE International Symposium on Circuits and Systems. 2004, pp 345-348, isbn 0-7803-8251-X, 4 p.Conference Paper

The effect of cluster packing and node duplication control in delay driven clusteringMEHRDAD ESLAMI DEHKORDI; BROWN, Stephen D.IEEE international conference on field-programmable technology. 2002, pp 227-233, isbn 0-7803-7574-2, 7 p.Conference Paper

A persistent diagnostic technique for unstable defectsSATO, Yasuo; YAMAZAKI, Iwao; YAMANAKA, Hiroki et al.Proceedings - International Test Conference. 2002, pp 242-249, issn 1089-3539, isbn 0-7803-7542-4, 8 p.Conference Paper

Proof regarding the NP-completeness of the unweighted complex-triangle elimination (CTE) problem for general adjacency graphsROY, S; BANDYOPADHYAY, S; MAULIK, U et al.IEE proceedings. Computers and digital techniques. 2001, Vol 148, Num 6, pp 238-244, issn 1350-2387Article

Reverse engineering of data simulationHUNG LIANG.SPIE proceedings series. 2003, pp 710-717, isbn 0-8194-4996-2, 8 p.Conference Paper

Generic hierarchical engine for mask data preparationKALUS, Christian K; RÖSSL, Wolfgang; SCHNITKER, Uwe et al.SPIE proceedings series. 2002, pp 66-74, isbn 0-8194-4517-7, 9 p.Conference Paper

Yield/reliability enhancement using automated minor layout modificationsALLAN, Gerard A.ASMC proceedings. 2002, pp 252-261, issn 1078-8743, isbn 0-7803-7158-5, 10 p.Conference Paper

Network flow based buffer planningXIAOPING TANG; WONG, D. F.Integration (Amsterdam). 2001, Vol 30, Num 2, pp 143-155, issn 0167-9260Article

Display matrix of three-electrode active MDMDM-elementsVOROBYOVA, A. I; OUTKINA, E. A.SPIE proceedings series. 2001, pp 73-75, isbn 0-8194-4226-7Conference Paper

An approach to designing modular extensible linear arrays for regular algorithmsCHANG, P.-Y; TSAY, J.-C.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 212-216, issn 0018-9340Article

Minimum-congestion hypergraph embedding in a cycleGANLEY, J. L; COHOON, J. P.IEEE transactions on computers. 1997, Vol 46, Num 5, pp 600-602, issn 0018-9340Article

Defect-aware Reticle Floorplanning for EUV MasksALI KAGALWALLA, Abde; GUPTA, Puneet; HUR, Duck-Hyung et al.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 7974, issn 0277-786X, isbn 978-0-8194-8533-5, 79740Z.1-79740Z.10Conference Paper

Design and process integration for microelectronic manufacturing II (Santa Clara CA, 26-27 February 2004)Liebmann, Lars W.SPIE proceedings series. 2004, isbn 0-8194-5292-0, XVIII, 302 p, isbn 0-8194-5292-0Conference Proceedings

Prediction of design sensitivity to altPSM lithography across process windowLACOUR, Pat; COBB, Nick.SPIE proceedings series. 2004, pp 604-613, isbn 0-8194-5513-X, 2Vol, 10 p.Conference Paper

Estimating pre-placement FPGA interconnection requirementsKANNAN, Parivallal; BHATIA, Dinesh.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 869-874, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

Modification of existing chip layout for yield and reliability improvement by computer aided design toolsLI, Mu-Jing; MATURI, Suryanarayana; DIXIT, Pankaj et al.SPIE proceedings series. 2003, pp 341-345, isbn 0-8194-4847-8, 5 p.Conference Paper

A layout compactor using a virtual grid representation and independent hardware platformMOURA, L. G; ANIDO, M. L; OLIVEIRA, C. E. T et al.Proceedings - Electrochemical Society. 2003, pp 222-232, issn 0161-6374, isbn 1-56677-389-X, 11 p.Conference Paper

Rapid inductive fault analysis for high-yield circuitsPLATTS, A; TAYLOR, D.Microelectronics journal. 2002, Vol 33, Num 3, pp 279-284, issn 0959-8324Article

Optimum mask and source patterns to print a given shapeROSENBLUTH, Alan E; BUKOFSKY, Scott; HIBBS, Michael et al.SPIE proceedings series. 2001, pp 486-502, isbn 0-8194-4032-9, 2VolConference Paper

New mask data verification method after optical proximity effect correctionOGAWA, Kazuhisa; ASHIDA, Isao; KAWAHIRA, Hiroichi et al.SPIE proceedings series. 2001, pp 186-193, isbn 0-8194-4111-2Conference Paper

High yield standard cell libraries: Optimization and modelingDRAGONE, Nicola; QUARANTELLI, Michele; BERTOLETTI, Massimo et al.Lecture notes in computer science. 2004, pp 129-137, issn 0302-9743, isbn 3-540-23095-5, 9 p.Conference Paper

  • Page / 15