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Results 1 to 25 of 3105

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Board level underfill for CSP applicationsVIJCHULATA, Prakorn.SPIE proceedings series. 2003, pp 368-373, isbn 0-8194-5189-4, 6 p.Conference Paper

Quantitative LGA/substrate assembly contact study from pressure sensitive film measurementsWEI ZOU; LONGWORTH, Hai.SPIE proceedings series. 2003, pp 807-812, isbn 0-8194-5189-4, 6 p.Conference Paper

Study of a laser microwelding process for microelectronics and packagingWEI HAN; PRYPUTNIEWICZ, Ryszard J.SPIE proceedings series. 2001, pp 713-716, isbn 0-8194-4317-4Conference Paper

Nonepoxy-based underfills for CSP assemblyMORGANELLI, Paul; FRIMANSON, Rob; LAFFEY, Matthew et al.SPIE proceedings series. 2003, pp 922-926, isbn 0-8194-5189-4, 5 p.Conference Paper

Front end compatible wafer level CSP-technology for FR- and HT-applicationsBURGER, Klaus.SPIE proceedings series. 2003, pp 714-718, isbn 0-8194-5189-4, 5 p.Conference Paper

An objective assessment of printed and plated bumping technologiesLING, Jamin; SHIN, Won-Sun; LAW, Edward et al.SPIE proceedings series. 2003, pp 906-909, isbn 0-8194-5189-4, 4 p.Conference Paper

Latest development in chip scale package laser marking and micro laser markingBO GU.IEEE/CPMT/SEMI international electronics manufacturing technology. Symposium. 2004, pp 144-146, isbn 0-7803-8582-9, 1Vol, 3 p.Conference Paper

Assembly and reliability issues associated with leadless chip scale packagesMUKADAM, Muffadal; MEILUNAS, Michael; BORGESEN, Peter et al.SPIE proceedings series. 2003, pp 900-905, isbn 0-8194-5189-4, 6 p.Conference Paper

New wafer level structure for stress free area array solder attachFILLION, R; MEYER, L; DUROCHER, K et al.SPIE proceedings series. 2003, pp 687-692, isbn 0-8194-5189-4, 6 p.Conference Paper

Bump wafer level packaging: A new packaging platform (not only) for memory productsHEDLER, Harry; MEYER, Thorsten; LEIBERG, Wolfgang et al.SPIE proceedings series. 2003, pp 681-686, isbn 0-8194-5189-4, 6 p.Conference Paper

Board level reliability of various stacked die chip scale package configurationsCARSON, Flynn; ZAHN, Bret; MITCHELL, Dianne et al.SPIE proceedings series. 2003, pp 894-899, isbn 0-8194-5189-4, 6 p.Conference Paper

Stencil printing technology for 100μm flip chip bumpingMANESSIS, Dionysios; PATZELT, Rainer; OSTMANN, Andreas et al.SPIE proceedings series. 2003, pp 241-246, isbn 0-8194-5189-4, 6 p.Conference Paper

Room temperature bond for wafer level packagingLINDNER, Paul; GLINSNER, Thomas; THANNER, Christine et al.SPIE proceedings series. 2003, pp 699-702, isbn 0-8194-5189-4, 4 p.Conference Paper

Self-constrained LTCC tapeLAUTZENHISER, Frans; AMAYA, Edmar.American Ceramic Society bulletin. 2002, Vol 81, Num 10, pp 27-32, issn 0002-7812Article

An approach to custom CSP package fabricationSOUCY, Joseph W; CLAUSEN, Henry G; BUSA, Charles E et al.SPIE proceedings series. 2003, pp 113-117, isbn 0-8194-5189-4, 5 p.Conference Paper

A study of non-flow under-fill flip-chip bonding process for LCP based cof componentsFURUKI, Satoshi; TAKAHASHI, Hiroyuki; HATANO, Chihiro et al.SPIE proceedings series. 2003, pp 87-92, isbn 0-8194-5189-4, 6 p.Conference Paper

Novel microstructuring technology for glass on silicon and glass-substratesMUND, Dietrich; LEIB, Jurgen.Proceedings - Electronic Components Conference. 2004, issn 0569-5503, isbn 0-7803-8365-6, 2Vol, Vol 1, 939-942Conference Paper

Wafer-level packaging of optoelectronic chips using sea of leads electrical and optical I/O interconnectionsBAKIR, Muhannad S; MEINDL, James D.Lasers and Electro-optics Society. 2004, isbn 0-7803-8557-8, 2Vol, Vol2, 583-584Conference Paper

Reliability of a wafer level packaging method with plastic-core solder bumps: Utilizing Sn-Ag solder at 0.3 mm diameterSUMIKAWA, Masato; MURAYAMA, Rina; OGAWA, Masashi et al.SPIE proceedings series. 2003, pp 693-698, isbn 0-8194-5189-4, 6 p.Conference Paper

Wafer level packaging technology for low-loss on-chip transmission lines and inductorsCARCHON, G; SUN, X; DE RAEDT, W et al.SPIE proceedings series. 2003, pp 167-172, isbn 0-8194-5189-4, 6 p.Conference Paper

Lead-free solder bump technologies for flip-chip electronic packaging applicationsKARIM, Zaheed S; CHOW, Alice; CHEUNG, Edwin et al.SPIE proceedings series. 2002, pp 570-575, isbn 0-8194-4500-2, 2VolConference Paper

Reliability evaluation for solder joints in embed electronic packageYAMABE, Masashi; QIANG YU; SHIBUTANI, Tadahiro et al.Proceedings of SPIE, the International Society for Optical Engineering. 2008, Vol 6798, pp 67980S.1-67980S.10, issn 0277-786X, isbn 978-0-8194-6969-4 0-8194-6969-6, 1VolConference Paper

Numerical simulation of underfill cure evolution in chip-scale-package (CSP) manufacturing processGOMATAM, Rajesh R; COULTER, John P.SPIE proceedings series. 2003, pp 916-921, isbn 0-8194-5189-4, 6 p.Conference Paper

Design guidelines to implement Six Sigma in assembly process yield of area array solder interconnect packagesCHUNHO KIM; BALDWIN, Daniel F.Proceedings - Electronic Components Conference. 2002, pp 1560-1568, issn 0569-5503, isbn 0-7803-7430-4, 9 p.Conference Paper

No-fault-found and intermittent failures in electronic productsHAIYU QI; GANESAN, Sanka; PECHT, Michael et al.Microelectronics and reliability. 2008, Vol 48, Num 5, pp 663-674, issn 0026-2714, 12 p.Article

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