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Three-dimensional Integrated Circuits DesignYUAN XIE; MARCHAL, Pol.IET computers & digital techniques (Print). 2011, Vol 5, Num 3, issn 1751-8601, 63 p.Serial Issue

VLSI circuits and systems V (18-20 April 2011, Prague, Czech Republic)Riesgo, Teresa; Torre-Arnanz, Eduardo de la.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 8067, issn 0277-786X, isbn 978-0-8194-8656-1, 1 vol, isbn 978-0-8194-8656-1Conference Proceedings

Statistical analysis of gate CD variation for yield optimizationHOLWILL, Juliet; KYE, Jongwook; YI ZOU et al.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 65211P.1-65211P.8, issn 0277-786X, isbn 978-0-8194-6640-2Conference Paper

A tale of two nets : Studies of wirelength progression in physical designKAHNG, Andrew B; REDA, Sherief.International Workshop on System-Level Interconnect Prediction. 2006, pp 17-24, isbn 1-595-93255-0, 8 p.Conference Paper

17th International Conference on VLSI Design (concurrently with the 3rd International Conference on Embedded Systems Design)International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, isbn 0-7695-2072-3, 1Vol, XXXV-1095 p, isbn 0-7695-2072-3Conference Proceedings

International Symposium for Quality Electronic Design 2007WRIGHT, Peter; HECTOR, Scott.IEEE transactions on semiconductor manufacturing. 2008, Vol 21, Num 1, pp 1-71, issn 0894-6507, 70 p.Conference Paper

Design for manufacturability through design-process integration (28 February-2 March 2007, San Jose, California, USA)Wong, Alfred Kwok-Kit; Singh, Vivek K.Proceedings of SPIE, the International Society for Optical Engineering. 2007, issn 0277-786X, isbn 978-0-8194-6640-2, 1 v. (various pagings), isbn 978-0-8194-6640-2Conference Proceedings

Double patterning technology : Process-window analysis in a many-dimensional spaceSEZGINER, Apo; YENIKAYA, Bayram.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 652113.1-652113.9, issn 0277-786X, isbn 978-0-8194-6640-2Conference Paper

Integrated circuit and system design (power and timing modeling, optimization and simulation)Macii, Enrico; Paliouras, Vassilis; Koufopavlou, Odysseas et al.Lecture notes in computer science. 2004, issn 0302-9743, isbn 3-540-23095-5, XVI, 906 p, isbn 3-540-23095-5Conference Proceedings

SPECIAL ISSUE ON THERMAL- AND POWER-AWARE DESIGN OF 2D/3D ICSTAN, Sheldon; ATIENZA, David.Integration (Amsterdam). 2013, Vol 46, Num 1, issn 0167-9260, 90 p.Serial Issue

ICCD 2004 (IEEE International Conference on Computer Design)IEEE International Conference on Computer Design. 2004, isbn 0-7695-2231-9, 1Vol, XVIII-578 p, isbn 0-7695-2231-9Conference Proceedings

Quality improvement methods for system-level stimuli generationEMEK, Roy; JAEGER, Itai; KATZ, Yoav et al.IEEE International Conference on Computer Design. 2004, pp 204-206, isbn 0-7695-2231-9, 1Vol, 3 p.Conference Paper

Special Issue on 23rd IEEE International Conference on VLSI Design, Bangalore, India, 3-7 January 2010BHUNIA, Swarup.Journal of low power electronics (Print). 2010, Vol 6, Num 3, issn 1546-1998, 96 p.Serial Issue

22nd IEEE International Conference on VLSI Design, New Delhi, India, 2009PANDA, Rajendran; PANDA, Preeti Ranjan.Journal of low power electronics (Print). 2009, Vol 5, Num 3, issn 1546-1998, 154 p.Serial Issue

Property refinement techniques for enhancing coverage of formal property verificationBASU, Prasenjit; DASGUPTA, Pallab; CHAKRABARTI, P. P et al.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 109-114, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

Trends in systematic non-particle yield loss mechanisms and the implication for IC designBERGLUND, C. N.SPIE proceedings series. 2003, pp 395-403, isbn 0-8194-4847-8, 9 p.Conference Paper

Layout Electrical cooptimization for increased tolerance to process variationsRIVIERE-CAZAUX, Lionel; HURAT, Philippe; KASTHURI, Bala et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7275, issn 0277-786X, isbn 978-0-8194-7528-2 0-8194-7528-9, 1Vol, 727506.1-727506.7Conference Paper

A New Flexible Algorithm for Random Yield ImprovementSINHA, Subarna; QING SU; LINNI WEN et al.IEEE transactions on semiconductor manufacturing. 2008, Vol 21, Num 1, pp 14-21, issn 0894-6507, 8 p.Conference Paper

Application of statistical tools and methods for high density substrate process developmentMARTIN, Lara J; FREI, John.Proceedings - Electronic Components Conference. 2002, pp 690-699, issn 0569-5503, isbn 0-7803-7430-4, 10 p.Conference Paper

Design for manufacturability through design-process integration III (26-27 February 2009, San Jose, California, United States)Singh, Vivek K; Rieger, Michael L.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7275, issn 0277-786X, isbn 978-0-8194-7528-2 0-8194-7528-9, 1Vol, various pagings, isbn 978-0-8194-7528-2 0-8194-7528-9Conference Proceedings

Reliability-and process-variation aware design of integrated circuitsALAM, M.Microelectronics and reliability. 2008, Vol 48, Num 8-9, pp 1114-1122, issn 0026-2714, 9 p.Conference Paper

Ant colony optimization technique for macrocell overlap removalALUPOAEI, Stelian; KATKOORI, Srinivas.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 963-968, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

System design of chip and board level optical interconnectsPLANT, David V.Bipolar/BiCMOS Circuits and Technology Meetings. 2004, pp 72-78, isbn 0-7803-8618-3, 1Vol, 7 p.Conference Paper

The certainty of uncertainty: Randomness in nanometer designHONGLIANG CHANG; HAIFENG QIAN; SAPATNEKAR, Sachin S et al.Lecture notes in computer science. 2004, pp 36-47, issn 0302-9743, isbn 3-540-23095-5, 12 p.Conference Paper

Physical fundamentals of external transient latch-up and corrective actionsDOMANSKI, K; POLTORAK, B; BARGSTÄDT-FRANKE, S et al.Microelectronics and reliability. 2006, Vol 46, Num 5-6, pp 689-701, issn 0026-2714, 13 p.Conference Paper

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