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Development of an Enterprise-Wide Yield Management System Using Critical Area Analysis for High-Product-Mix Semiconductor ManufacturingHAMAMURA, Yuichi; MATSUMOTO, Chizu; KANEKO, Shun'ichi et al.IEICE transactions on electronics. 2009, Vol 92, Num 1, pp 144-152, issn 0916-8524, 9 p.Article

A new transistor folding algorithm applied to an automatic full-custom layout generation toolBASTIAN, Fabricio B; LAZZARI, Cristiano; GUNTZEL, Jose Luis et al.Lecture notes in computer science. 2004, pp 732-741, issn 0302-9743, isbn 3-540-23095-5, 10 p.Conference Paper

Inspection of aggressive OPC using aerial image-based mask inspectionHSU, Luke T. H; HUNG, Johnson C. C; HSIEH, H. C et al.SPIE proceedings series. 2003, pp 357-363, isbn 0-8194-4996-2, 7 p.Conference Paper

Generating random benchmark circuits for floorplanningTAO WAN; CHRZANOWSKA-JESKE, Malgorzata.IEEE International Symposium on Circuits and Systems. 2004, pp 345-348, isbn 0-7803-8251-X, 4 p.Conference Paper

The effect of cluster packing and node duplication control in delay driven clusteringMEHRDAD ESLAMI DEHKORDI; BROWN, Stephen D.IEEE international conference on field-programmable technology. 2002, pp 227-233, isbn 0-7803-7574-2, 7 p.Conference Paper

A persistent diagnostic technique for unstable defectsSATO, Yasuo; YAMAZAKI, Iwao; YAMANAKA, Hiroki et al.Proceedings - International Test Conference. 2002, pp 242-249, issn 1089-3539, isbn 0-7803-7542-4, 8 p.Conference Paper

Proof regarding the NP-completeness of the unweighted complex-triangle elimination (CTE) problem for general adjacency graphsROY, S; BANDYOPADHYAY, S; MAULIK, U et al.IEE proceedings. Computers and digital techniques. 2001, Vol 148, Num 6, pp 238-244, issn 1350-2387Article

Non-Uniform Yield Optimization for Integrated Circuit Layout Considering Global InteractionsANDRES TORRES, J; PIKUS, Fedor G.Proceedings of SPIE, the International Society for Optical Engineering. 2008, Vol 7122, issn 0277-786X, isbn 978-0-8194-7355-4 0-8194-7355-3, 71223R.1-71223R.8, 2Conference Paper

Hexagonal three-layer channel routingXUEHOU TAN; XIAOYU SONG.Information processing letters. 1995, Vol 55, Num 4, pp 223-228, issn 0020-0190Article

Advanced Method for Defect Characterization Using Fail Bit Analysis and Critical Area SimulationMATSUMOTO, Chizu; HAMAMURA, Yuichi; CHIDA, Takafumi et al.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 2, pp 151-157, issn 0894-6507, 7 p.Conference Paper

Fully Understanding the Mechanism of Misalignment-Induced Narrow-Transistor Failure and Carefully Evaluating the Misalignment-Tolerant SRAM-Cell LayoutNAKAI, Satoshi; MIYAZAKI, Yasumori; YASUDA, Makoto et al.IEEE transactions on semiconductor manufacturing. 2012, Vol 25, Num 3, pp 317-322, issn 0894-6507, 6 p.Conference Paper

Reverse engineering of data simulationHUNG LIANG.SPIE proceedings series. 2003, pp 710-717, isbn 0-8194-4996-2, 8 p.Conference Paper

Generic hierarchical engine for mask data preparationKALUS, Christian K; RÖSSL, Wolfgang; SCHNITKER, Uwe et al.SPIE proceedings series. 2002, pp 66-74, isbn 0-8194-4517-7, 9 p.Conference Paper

Yield/reliability enhancement using automated minor layout modificationsALLAN, Gerard A.ASMC proceedings. 2002, pp 252-261, issn 1078-8743, isbn 0-7803-7158-5, 10 p.Conference Paper

Network flow based buffer planningXIAOPING TANG; WONG, D. F.Integration (Amsterdam). 2001, Vol 30, Num 2, pp 143-155, issn 0167-9260Article

Display matrix of three-electrode active MDMDM-elementsVOROBYOVA, A. I; OUTKINA, E. A.SPIE proceedings series. 2001, pp 73-75, isbn 0-8194-4226-7Conference Paper

An approach to designing modular extensible linear arrays for regular algorithmsCHANG, P.-Y; TSAY, J.-C.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 212-216, issn 0018-9340Article

Minimum-congestion hypergraph embedding in a cycleGANLEY, J. L; COHOON, J. P.IEEE transactions on computers. 1997, Vol 46, Num 5, pp 600-602, issn 0018-9340Article

High yield standard cell libraries: Optimization and modelingDRAGONE, Nicola; QUARANTELLI, Michele; BERTOLETTI, Massimo et al.Lecture notes in computer science. 2004, pp 129-137, issn 0302-9743, isbn 3-540-23095-5, 9 p.Conference Paper

Constrained floorplanning with whitespaceYAN FENG; MEHTA, Dinesh.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 969-974, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

Floorplan classification algorithmsKUN GAO; MEHTA, Dinesh P.International Conference on Embedded Systems DesignInternational Conference on VLSI Design. 2004, pp 975-980, isbn 0-7695-2072-3, 1Vol, 6 p.Conference Paper

Advanced data preparation and design automationSCHELLENBERG, F. M.SPIE proceedings series. 2002, pp 54-65, isbn 0-8194-4517-7, 12 p.Conference Paper

Cell-based layout techniques supporting gate-leve voltage scaling for low powerCHINGWEI YEH; KANG, Yin-Shuin.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 6, pp 983-986, issn 1063-8210Article

Floating steiner treesSARRAFZADEH, M; LIN, W.-L; WONG, C. K et al.IEEE transactions on computers. 1998, Vol 47, Num 2, pp 197-211, issn 0018-9340Article

Node-covering, error-correcting codes and multiprocessors with very high average fault toleranceDUTT, S; MAHAPATRA, N. R.IEEE transactions on computers. 1997, Vol 46, Num 9, pp 997-1015, issn 0018-9340Article

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