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Position statement: TAPs all over my chipsOAKLAND, Steven F.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1192Conference Paper

Board test is not maturePARKER, Kenneth P.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1238Conference Paper

Panel: board test and ITC: what does the future hold?LOBETTI-BODONI, Monica.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1239Conference Paper

Board test: Wanted dead or aliveROBINSON, Gordon D.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1236Conference Paper

13th Asian test symposium (Kenting, Taiwan, November 15-17, 2004, proceedings)Asian test symposium. 2004, isbn 0-7695-2235-1, 1Vol, XXVI-465 p, isbn 0-7695-2235-1Conference Proceedings

Trends in testing integrated circuitsVERMEULEN, Bart; HORA, Camelia; KRUSEMAN, Bram et al.International Test Conference. 2004, pp 688-697, isbn 0-7803-8580-2, 1Vol, 10 p.Conference Paper

Is ITC bored with board test?BUTLER, Kenneth M.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1237Conference Paper

Is board test worth talking about?EKLOW, Bill.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1235Conference Paper

TAPS all over my chip! So now what do i do?VERMEULEN, Bart.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1190Conference Paper

TAPS all over my chips - position statementMCLAURIN, Teresa L.Proceedings - International Test Conference. 2002, issn 1089-3539, isbn 0-7803-7542-4, p. 1193Conference Paper

Self-checking comparator with one periodic outputKUNDU, S; SOGOMONYAN, E. S; GOESSEL, M et al.IEEE transactions on computers. 1996, Vol 45, Num 3, pp 379-380, issn 0018-9340Article

Design and implementation of self-testable full range window comparatorWONG, Mike W. T; YUBIN ZHANG.Asian test symposium. 2004, pp 314-318, isbn 0-7695-2235-1, 1Vol, 5 p.Conference Paper

Bipolar SCR ESD protection in a 0.25 μm Si-Ge process using subcollector region modificationVASHCHENKO, V. A; CONCANNON, A; TER BEEK, M et al.IEEE international reliability physics symposium. 2004, pp 469-473, isbn 0-7803-8315-X, 1Vol, 5 p.Conference Paper

Abstraction techniques for validation coverage analysis and test generationMOUNDANOS, D; ABRAHAM, J. A; HOSKOTE, Y. V et al.IEEE transactions on computers. 1998, Vol 47, Num 1, pp 2-14, issn 0018-9340Article

Aliasing error for a mask ROM built-in self-testIWASAKI, K; NAKAMURA, S.IEEE transactions on computers. 1996, Vol 45, Num 3, pp 270-277, issn 0018-9340Article

Rapid and energy-efficient testing for embedded coresYINHE HAN; YU HU; HUAWEI LI et al.Asian test symposium. 2004, pp 8-13, isbn 0-7695-2235-1, 1Vol, 6 p.Conference Paper

The algorithm for parallel calibration based on fixed priority in the multi-parametric calibration systemSUN, Qun; MENG, Xiaofeng; ZHENG, Wei et al.Proceedings of SPIE, the International Society for Optical Engineering. 2006, pp 63581U.1-63581U.5, issn 0277-786X, isbn 0-8194-6453-8, 2VolConference Paper

Flexible embedded test solution for high-speed analogue front-end architectures : Analogue and mixed-signal test for systems on chipLECHNER, A; BURBIDGE, M. J; RICHARDSON, A. M. D et al.IEE proceedings. Circuits, devices and systems. 2004, Vol 151, Num 4, pp 359-369, issn 1350-2409, 11 p.Article

Techniques for finding Xs in test sequences for sequential circuits and applications to test length/power reductionHIGAMI, Yoshinobu; KAJIHARA, Seiji; KOBAYASHI, Sin-Ya et al.Asian test symposium. 2004, pp 46-49, isbn 0-7695-2235-1, 1Vol, 4 p.Conference Paper

Optimal Self-Testing Embedded parity checkersNIKOLOS, D.IEEE transactions on computers. 1998, Vol 47, Num 3, pp 313-321, issn 0018-9340Article

ESD testing of devices, ICs and systemsSMEDES, T.Microelectronics and reliability. 2009, Vol 49, Num 9-11, pp 941-945, issn 0026-2714, 5 p.Article

International Conference on Design & Test of Integrated Systems in Nanoscale TechnologyMASMOUDI, Mohamed; RENOVELL, Michel; GIRARD, Patrick et al.International journal of electronics. 2008, Vol 95, Num 3, issn 0020-7217, 128 p.Conference Proceedings

Crosstalk delay analysis of a 0.13-μm-node test chip and precise gate-level simulation technologySASAKI, Yasuhiko; SATOH, Mitsumasa; KURAMOTO, Masaru et al.2002 symposium on VLSI circuits. 2002, pp 212-215, isbn 0-7803-7310-3, 4 p.Conference Paper

22nd IEEE VLSI test symposium (Napa Valley CA, 25-29 April 2004)IEEE VLSI test symposium. 2004, isbn 0-7695-2134-7, 1Vol, XXVII-406 p, isbn 0-7695-2134-7Conference Proceedings

Compendia of TID and SEE test results of integrated circuitsLAYTON, Phil; WILLIAMSON, Gale; GILBERT, Charlie et al.IEEE radiation effects data workshop. 2004, pp 6-9, isbn 0-7803-8697-3, 1Vol, 4 p.Conference Paper

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