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A diagonal active-area stacked capacitor DRAM cell with storage capacitor on bit lineKIMURA, S; KAWAMOTO, Y; KURE, T et al.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 3, pp 737-743, issn 0018-9383, 1Article

Charge transport and storage of low programming voltage sonos/monos memory devicesLIBSCH, F. R; WHITE, M. H.Solid-state electronics. 1990, Vol 33, Num 1, pp 105-126, issn 0038-1101Article

New stack capacitor for dynamic data storage in polysilicon active matrix arraysTIAO-YUAN HUANG; LEWIS, A. G; I-WEI WU et al.IEEE electron device letters. 1990, Vol 11, Num 3, pp 116-119, issn 0741-3106Article

Oxides grown on textured single-crystal silicon ― dependence on process and application in EEPROM'sFONG, Y; WU, A. T.-T; HU, C et al.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 3, pp 583-590, issn 0018-9383, 1Article

Double-level polysilicon NMOS technology for the 16 kbit random access memory MMN 4116BARSAN, R; COBIANU, C; CONDRIUC, L et al.Revue roumaine des sciences techniques. Electrotechnique et énergétique. 1989, Vol 34, Num 1, pp 47-55, issn 0035-4066Article

Testability of parity checkersSAMIHA MOURAD; MCCLUSKEY, E. J.IEEE transactions on industrial electronics (1982). 1989, Vol 36, Num 2, pp 254-262, issn 0278-0046Article

Graphic data processor GDP «HD64400»TAKEDA, H; MAEJIMA, H; KATSURA, K et al.Hitachi review. 1989, Vol 38, Num 1, pp 31-38, issn 0018-277XArticle

High-performance floating-point processing unitMORINAGA, S; KAWASAKI, S.Hitachi review. 1989, Vol 38, Num 1, pp 25-30, issn 0018-277XArticle

120-ns 128K×8-bit/64K×16-bit CMOS EEPROM'sTERADA, Y; KOBAYASHI, K; NAKAYAMA, T et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1244-1249, issn 0018-9200Article

30-ps 7.5-GHz GaAs MESFET macrocell arrayINO, M; TOGASHI, M; HORIGUCHI, S et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1265-1270, issn 0018-9200Article

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level convertersMATSUI, M; MOMOSE, H; URAKAWA, Y et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1226-1232, issn 0018-9200Article

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cellMOMODOMI, M; ITOH, Y; MASUOKA, F et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1238-1243, issn 0018-9200Article

Analysis and modeling of on-chip high-voltage generator circuits for use in EEPROM circuitsWITTERS, J. S; GROESENEKEN, G; MAES, H. E et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1372-1380, issn 0018-9200Article

Design for reducing alpha-particle-induced soft errors in ECL logic circuitryOKABE, M; TATSUKI, M; ARIMA, Y et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1397-1403, issn 0018-9200Article

Page-number of hypercubes and cube-connected cyclesKONOE, M; HAGIHARA, K; TOKURA, N et al.Systems and computers in Japan. 1989, Vol 20, Num 4, pp 34-47, issn 0882-1666Article

SST: scan self-test for sequential machinesWANG, L. T; MOURAD, S.IEE proceedings. Part E. Computers and digital techniques. 1989, Vol 136, Num 6, pp 569-574, issn 0143-7062Article

Substrate current reduction techniques for BiCMOS DRAMKAWAHARA, T; KITSUKAWA, G; HIGUCHI, H et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1381-1389, issn 0018-9200Article

VLSI implementation for digital image and video processing applicationsHAMID GHARAVI, Ed; PIRSCH, P; YASUDA, H et al.IEEE transactions on circuits and systems. 1989, Vol 36, Num 10, pp 1257-1375, issn 0098-4094Serial Issue

VLSI testing and testability considerations an overviewHURST, S. L.Microelectronics. 1988, Vol 19, Num 4, pp 57-69, issn 0026-2692Article

Eine neue Speicherzelle mit Ladungsverstärkung für ULSI-dRAM = Nouvelle cellule à mémoire à amplification de charge pour mémoire RAM dynamique ULSI = New charge amplification memory cell for ULSI dynamic RAMGEITNER, V; KOSCH, J.Wissenschaftliche Zeitschrift der Technischen Universität Dresden. 1988, Vol 37, Num 3, pp 187-188, issn 0043-6925Article

A GaAs 4-bit adder-accumulator circuit for direct digital synthesisEKROOT, C. G; LONG, S. I.IEEE journal of solid-state circuits. 1988, Vol 23, Num 2, pp 573-580, issn 0018-9200Article

A high-speed line-memory LSI for multiple applicationsAIDA, T; ABE, M; GOTO, K et al.NHK Laboratories Note. 1988, Num 362, pp 1-15, issn 0027-657XArticle

A new static memory cell based on the negative resistance characteristic of a UJTRAMKUMAR, K; SATYAM, M.Microelectronics. 1988, Vol 19, Num 2, pp 51-56, issn 0026-2692Article

Design for GaAs high-speed digital ICINO, M; TOGASHI, M; SUTOH, H et al.Review of the electrical communication laboratories. 1988, Vol 36, Num 6, pp 509-515, issn 0029-067XArticle

Multiple parallel-acting iterative arrays for fast divisionMANDELBAUM, D. M.International journal of electronics. 1988, Vol 64, Num 6, pp 885-896, issn 0020-7217Article

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