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Results 1 to 25 of 130

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Cost-density analysis of interconnectionsMESSNER, G.IEEE transactions on components, hybrids, and manufacturing technology. 1987, Vol 10, Num 2, pp 143-151, issn 0148-6411Article

Short-term forecasting in electronicsMILOJKOVIC, Jelena; LITOVSKI, Vančo.International journal of electronics. 2011, Vol 98, Num 1-3, pp 161-172, issn 0020-7217, 12 p.Article

Large-output-force out-of-plane MEMS actuator arrayFUKUSHIGE, T; HATA, S; SHIMOKOHBE, A et al.SPIE proceedings series. 2004, pp 240-249, isbn 0-8194-5169-X, 10 p.Conference Paper

Field reduction regions for compact high-voltage IC'sSUGAWARA, Y; KAMEI, T.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 8, pp 1816-1822, issn 0018-9383, 1Article

Le câblage par fil: une nouvelle piste pour les cartes à CMS = The wiring: a new track for SMC boardsMesures (1983). 1987, Vol 52, Num 12, pp 55-61, issn 0755-219X, 4 p.Article

Failure analysis techniques for a 3D worldHENDERSON, Christopher L.Microelectronics and reliability. 2013, Vol 53, Num 9-11, pp 1171-1178, issn 0026-2714, 8 p.Conference Paper

Fifty Years of Moore's LawMACK, Chris A.IEEE transactions on semiconductor manufacturing. 2011, Vol 24, Num 2, pp 202-207, issn 0894-6507, 6 p.Article

Future Directions for CMOS Device Technology Development from a System Application PerspectiveNINE, Tak H.Proceedings of SPIE, the International Society for Optical Engineering. 2007, pp 652003.1-652003.5, issn 0277-786X, isbn 978-0-8194-6639-6Conference Paper

Analysis of the silicon technology roadmap : How far can CMOS go ? : Les défis techniques de la microélectronique = Challenges in microelectronicsSKOTNICKI, Thomas.Comptes rendus de l'Académie des sciences. Série IV, Physique, astrophysique. 2000, Vol 1, Num 7, pp 885-909, issn 1296-2147Article

Algorithm for incremental compaction of geometrical layoutsNANDY, S. K; PATNAIK, L. M.Computer-aided design. 1987, Vol 19, Num 5, pp 257-265, issn 0010-4485Article

Planar CMOS to multi-gate layout conversion for maximal fin utilizationWIMER, Shmuel.Integration (Amsterdam). 2014, Vol 47, Num 1, pp 115-122, issn 0167-9260, 8 p.Article

A 32 GBit/s communication SoC for a waferscale neuromorphic systemSCHOLZE, Stefan; EISENREICH, Holger; HÖPPNER, Sebastian et al.Integration (Amsterdam). 2012, Vol 45, Num 1, pp 61-75, issn 0167-9260, 15 p.Article

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A ReviewSACCHETTO, Davide; DE MICHELI, Giovanni; LEBLEBICI, Yusuf et al.Proceedings of the IEEE. 2012, Vol 100, Num 6, pp 2008-2020, issn 0018-9219, 13 p.Article

High density vertical silicon NEM switches with CMOS-compatible fabricationNG, E. J; SOON, J. B. W; SINGH, N et al.Electronics letters. 2011, Vol 47, Num 13, pp 759-760, issn 0013-5194, 2 p.Article

Moore's Law in the Innovation EraBOHR, Mark.Proceedings of SPIE, the International Society for Optical Engineering. 2011, Vol 7974, issn 0277-786X, isbn 978-0-8194-8533-5, 797402.1-7974028Conference Paper

La plateforme ASTEP du Plateau de Bure Tests en environnement radiatif naturel de composants et circuits électroniques : Effets des radiations naturelles sur l'électronique au niveau atmosphérique et terrestre = The Plateau de Bure ASTEP Platform. Test in Natural Radiation Environment of Electronic Components and Circuits : Effects of Natural Radiation on Electronics in Air and LandAUTAN, Jean-Luc; MUNTEANU, Daniela; SAUZE, Sébastien et al.REE. Revue de l'électricité et de l'électronique. 2010, Num 3, issn 1265-6534, 39-50, 74 [13 p.]Article

Nanoimprint for future non-volatile memory and logic devicesMEIER, M; NAUENHEIM, C; GILLES, S et al.Microelectronic engineering. 2008, Vol 85, Num 5-6, pp 870-872, issn 0167-9317, 3 p.Conference Paper

Study of flow visualization in stacked-Chip Scale Packages (S-CSP)KHALIL ABDULLAH, M; ABDULLAH, M. Z; KAMARUDIN, S et al.International communications in heat and mass transfer. 2007, Vol 34, Num 7, pp 820-828, issn 0735-1933, 9 p.Article

Majority logic gate for magnetic quantum-dot cellular automataIMRE, A; CSABA, G; JI, L et al.Science (Washington, D.C.). 2006, Vol 311, Num 5758, pp 205-208, issn 0036-8075, 4 p.Article

CMOS optoelectronicsLIU, C. W; HSU, B.-C.Proceedings - Electrochemical Society. 2004, pp 383-395, issn 0161-6374, isbn 1-56677-406-3, 13 p.Conference Paper

Micromachining of multi-thickness sensor-array structures with dual-stage etching technologyXINXIN LI; MINHANG BAO.Journal of micromechanics and microengineering (Print). 2001, Vol 11, Num 3, pp 239-244, issn 0960-1317Article

A tale of great expectations, snake oil, and system chipsBURSKY, D.Electronic design. 1999, Vol 47, Num 1, pp 79-83, issn 0013-4872Article

Asymptotic importance samplingMAES, M. A; BREITUNG, K; DUPUIS, D. J et al.Structural safety. 1993, Vol 12, Num 3, pp 167-186, issn 0167-4730Article

Estimation des performances des circuits intégrés. Application à la commutation ATM = Performances estimation of integrated circuits application to ATM switchingLARDY, J.-L.Annales des télécommunications. 1993, Vol 48, Num 3-4, pp 181-195, issn 0003-4347Article

Asymmetric chevron type junctions for hybrid bubble memory devices with 16-Mbit/cm2 storage densitySATO, T; IKEDA, T; SUZUKI, R et al.IEEE transactions on magnetics. 1988, Vol 24, Num 3, pp 2068-2073, issn 0018-9464Article

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