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KARNAUGH-DIAGRAMM SICHTBAR GEMACHT = LA VISUALISATION DU DIAGRAMME DE KARNAUGHVERCAMMEN F.1978; ELEKTRONIK; DEU; DA. 1978; VOL. 27; NO 12; PP. 123Article

KOMBINATORISCHE NETZWERKE MIT SPEZIELLEN ZUVERLAESSIGKEITSEIGENSCHAFTEN = LES RESEAUX COMBINATOIRES A CARACTERISTIQUES SPECIALES DE FIABILITEUHLIG D; WIEDEMUTH D.1979; NACHR.-TECH. ELEKTRON.; DDR; DA. 1979; VOL. 29; NO 8; PP. 326-328; BIBL. 2 REF.Article

A TRUE KARNAUGH MAP DISPLAY UNITHURST SL.1979; ELECTRON. ENGNG; GBR; DA. 1979; VOL. 51; NO 617; PP. 57-61; (3 P.)Article

Improved variable-entered Karnaugh map proceduresRUSHDI, A. M.Computers & electrical engineering. 1987, Vol 13, Num 1, pp 41-52, issn 0045-7906Article

Switching functions and solid geometrical modelerSHPITALNI, M.Proceedings of the IEEE. 1984, Vol 72, Num 1, pp 136-137, issn 0018-9219Article

KARNAUGH MAP EXTENDED TO SIX OR MORE VARIABLESHALDER AK.1982; ELECTRONICS LETTERS; ISSN 0013-5194; GBR; DA. 1982; VOL. 18; NO 20; PP. 868-870; BIBL. 4 REF.Article

GRAPHICAL EXHAUSTIVE ANALYSIS OF MINIMUM MUX SYNTHESIS OF SWITCHING FUNCTIONSLOTFI ZM; TOSSER AJ.1980; COMPUT. ELECTR. ENG.; ISSN 0045-7906; USA; DA. 1980; VOL. 7; NO 4; PP. 235-242; BIBL. 11 REF.Article

SAVING OF NAND/NOR GATES BY INHIBITION OR D-INHIBITIONRABEL M; DUBUS D; TOSSER A et al.1980; COMPUTER J.; GBR; DA. 1980; VOL. 23; NO 2; PP. 165-185; BIBL. 9 REF.Article

A dual algorithm for the satisfiability problemTANAKA, Y.Information processing letters. 1991, Vol 37, Num 2, pp 85-89, issn 0020-0190, 5 p.Article

Utilisation d'une table de Karnaugh pour minimiser un algorithme de décision binaire = Utilization of Karnaugh tables to minimize a binary decision algorithmBECHAR, H; TOSSER, A. J.International journal of electronics. 1984, Vol 56, Num 1, pp 79-94, issn 0020-7217Article

LOGIC DESIGN. I. BOOLEAN ALGEBRA AND KARNAUGH MAPS.HOLDSWORTH B; ZISSOS L.1977; WIRELESS WORLD; G.B.; DA. 1977; VOL. 83; NO 1493; PP. 51-54; BIBL. 3 REF.Article

ANWENDUN DER REKURSIVEN PROGRAMMIERUNG IN EINEM BOOLESCHEN FORMELRECHNER = EMPLOI DE LA PROGRAMMATION RECURSIVE DANS UN CALCULATEUR DE FORMULES BOOLEENNESKLEIN RD.1980; ELEKTRONIK; DEU; DA. 1980; VOL. 29; NO II; PP. 51-56Article

DETECTION ET ELIMINATION DU HASARD DANS LES CIRCUITS DE COMMUTATION MULTINIVEAUXHLAWICZKA A.1976; PRACE INST. MASZ. MAT.; POLSKA; DA. 1976; VOL. 18; NO 1; PP. 1-164; ABS. RUSSE ANGL.; BIBL. DISSEM.Serial Issue

SIEBENSEGMENT-ZU-BCD-KODEWANDLER = CONVERTISSEUR DE CODE BCD POUR AFFICHAGE A SEPT SEGMENTSBEYER M.1981; RADIO FERNS. ELEKTRON.; ISSN 0033-7900; DDR; DA. 1981; VOL. 30; NO 1; PP. 54; BIBL. 1 REF.Article

THE DERIVATION OF DISJUNCTIVE AND CONJUNCTIVE REDUCED BOOLEAN FORMS FROM DUAL KARNAUGH MAPSLOTFI Z; TOSSER AJ.1978; INTERNATION. J. ELECTRON.; GBR; DA. 1978; VOL. 44; NO 2; PP. 161-165; BIBL. 4 REF.Article

FORMAL LOGIC SYNTHESIS FOR THE PROGRAMMABLE LOGIC ARRAY.HEATH C; WILLIAMSON I.1976; ELECTRON. ENGNG; G.B.; DA. 1976; VOL. 48; NO 583; PP. 53-56; BIBL. 4 REF.Article

Efficient algorithm for logic design using multiplexersSOBHA SHANKAR, V.Electronics Letters. 1988, Vol 24, Num 3, pp 142-144, issn 0013-5194Article

Representations of logic functionsLEE, E. T.Kybernetes. 1995, Vol 24, Num 3, pp 50-58, issn 0368-492XArticle

Simplification of switching functions using variable-entered mapsGREEN, D. H.International journal of electronics. 1993, Vol 75, Num 5, pp 877-886, issn 0020-7217Article

Using variable-entered karnaugh maps to solve boolean equationsRUSHDI, Ali M.International journal of computer mathematics. 2001, Vol 78, Num 1, pp 23-38, issn 0020-7160Article

A fault model for PLA'sLIGTHART, M. M; STANS, R. J.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 2, pp 265-270, issn 0278-0070, 6 p.Article

Xiao map for minimization of boolean expressionXIAO YONG-XIN.International journal of electronics. 1987, Vol 63, Num 3, pp 353-358, issn 0020-7217Article

A general method in synthesis of pass-transistor circuitsMARKOVIC, D; NIKOLIC, B; OKLOBDIIJA, V. G et al.Microelectronics journal. 2000, Vol 31, Num 11-12, pp 991-998, issn 0959-8324Conference Paper

Two-level logic minimization : an overviewCOUDERT, O.Integration (Amsterdam). 1994, Vol 17, Num 2, pp 97-140, issn 0167-9260Article

Polarization-encoded optical shadow-casting programmable logic array: simultaneous generation of multiple outputsAWWAL, A. A. S; KARIM, M. A.Applied optics. 1988, Vol 27, Num 5, pp 932-936, issn 0003-6935Article

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