Addendum to synthesis of robust delay-fault testable circuits : TheoryDEVADAS, S; KEUTZER, K.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 4, pp 445-446, issn 0278-0070Article

Synthesis of robust delay-fault-testable circuits : practiceDEVADAS, S; KEUTZER, K.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 3, pp 277-300, issn 0278-0070Article

Code density optimization for embedded DSP processors using data compression techniquesLIAO, S. Y; DEVADAS, S; KEUTZER, K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1998, Vol 17, Num 7, pp 601-608, issn 0278-0070Article

Event suppression: Improving the efficiency of timing simulation for synchronous digital circuitsDEVADAS, S; KEUTZER, K; MALIK, S et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1994, Vol 13, Num 6, pp 814-822, issn 0278-0070Article

Delay-fault test generation and synthesis for testability under a standard scan design methodologyKWANG-TING CHENG; SRINIVAS DEVADAS; KEUTZER, K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 8, pp 1217-1231, issn 0278-0070Article

Computation of floating mode delay in combinational circuits : theory and algorithmsSRINIVAS DEVADAS; KEUTZER, K; SHARAD MALIK et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1993, Vol 12, Num 12, pp 1913-1923, issn 0278-0070Article

Estimation of power dissipation in CMOS combinational circuits using boolean function manipulationDEVADAS, S; KEUTZER, K; WHITE, J et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 3, pp 373-383, issn 0278-0070Article

Synthesis of hazard-free asynchronous circuits with bounded wire delaysLAVAGNO, L; KEUTZER, K; SANGIOVANNI-VINCENTELLI, A. L et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1995, Vol 14, Num 1, pp 61-86, issn 0278-0070Article

Synthesis for testability techniques for asynchronous circuitsKEUTZER, K; LAVAGNO, L; SANGIOVANNI-VINCENTELLI, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1995, Vol 14, Num 12, pp 1569-1577, issn 0278-0070Article

Path-delay-fault testability properties of multiplexor-based networksPRANAV ASHAR; SRINIVAS DEVADAS; KEUTZER, K et al.Integration (Amsterdam). 1993, Vol 15, Num 1, pp 1-23, issn 0167-9260Article

Necessary and sufficient conditions for hazard-free robust transistor stuck-open-fault testability in multilevel networksBRYAN, M. J; DEVADAS, S; KEUTZER, K et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1992, Vol 11, Num 6, pp 800-803, issn 0278-0070Article

Is redundancy necessary to reduce delay?KEUTZER, K; MALIK, S; SALDANHA, A et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1991, Vol 10, Num 4, pp 427-435, issn 0278-0070Article

Addendum to A Kernel-finding state assignment algorithm for multi-level logicWOLF, W; KEUTZER, K; AKELLA, J et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 8, pp 925-927, issn 0278-0070Article

Storage assignment to decrease code sizeLIAO, S; DEVADAS, S; KEUTZER, K et al.ACM transactions on programming languages and systems. 1996, Vol 18, Num 3, pp 235-253, issn 0164-0925Article

A disciplined approach to the development of platform architecturesAUGUST, D. I; KEUTZER, K; MALIK, S et al.Microelectronics journal. 2002, Vol 33, Num 11, pp 881-890, issn 0959-8324, 10 p.Conference Paper