Gate-level dual-threshold static power optimization methodology (GDSPOM) using path-based static timing analysis (STA) technique for SOC application : Power and timing modeling, optimization simulationCHUNG, B; KUO, J. B.Integration (Amsterdam). 2008, Vol 41, Num 1, pp 9-16, issn 0167-9260, 8 p.Article

A CMOS quadrature modulator for wireless communication ICLIN, P. F; LOU, J. H; KUO, J. B et al.IEEE transactions on circuits and systems. 1, Fundamental theory and applications. 1997, Vol 44, Num 6, pp 559-561, issn 1057-7122Article

A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 μm NMOS devicesCHEN, Y. G; KUO, J. B.IEEE transactions on computer-aided design of integrated circuits and systems. 1996, Vol 15, Num 2, pp 256-258, issn 0278-0070Article

2D device-level simulation study on D.C. and transient behavior of a SiGe-base HBT with a graded germanium profile in an ECL buffer operating at 77 KKUO, J. B; LU, T. C.Solid-state electronics. 1995, Vol 38, Num 2, pp 451-455, issn 0038-1101Article

Analytical threshold voltage formula including narrow-channel effects for VLSI mesa-isolated fully depleted ultrathin silicon-on-insulator N-channel metal-oxide-silicon-devicesKER-WEI SU; KUO, J. B.Japanese journal of applied physics. 1995, Vol 34, Num 8A, pp 4010-4019, issn 0021-4922, 1Article

An analytical SiGe-base HBT model and its effects on a BiCMOS inverter circuitLU, T. C; KUO, J. B.I.E.E.E. transactions on electron devices. 1994, Vol 41, Num 2, pp 272-276, issn 0018-9383Article

An analytical a-Si:H TFT DC/capacitance model using an effective temperature approach for deriving a switching time model for an inverter circuit considering deep and tail statesSHIAO-SHIEN CHEN; KUO, J. B.I.E.E.E. transactions on electron devices. 1994, Vol 41, Num 7, pp 1169-1178, issn 0018-9383Article

An analytical back-gate bias effect model for ultrathin SOI CMOS devicesJAI-HOON SIM; KUO, J. B.I.E.E.E. transactions on electron devices. 1993, Vol 40, Num 4, pp 755-765, issn 0018-9383Article

Analytical drain current model for a-Si:H TFTs by simultaneously considering localised deep and tail statesKUO, J. B; CHEN, C. S.Electronics Letters. 1993, Vol 29, Num 17, pp 1566-1568, issn 0013-5194Article

A closed-form analytical BJT forward transit time model considering bandgap-narrowing effects and concentrations-dependent diffusion coefficientsLU, T. C; KUO, J. B.Solid-state electronics. 1992, Vol 35, Num 9, pp 1374-1377, issn 0038-1101Article

An analytical delayed-turn-off model for buried-channel PMOS devices operating at 77 KJAI-HOON SIM; KUO, J. B.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 4, pp 939-947, issn 0018-9383Article

BiCMOS dynamic full adder circuit for high-speed parallel multipliersCHEN, H. P; LIAO, H. J; KUO, J. B et al.Electronics Letters. 1992, Vol 28, Num 12, pp 1124-1126, issn 0013-5194Article

Back gate bias effects on the pull-down transient behavior in an ultra-thin CMOS inverter operating at 300K and 77KKUO, J. B; LEE, W. C; SIM, J. H et al.Solid-state electronics. 1992, Vol 35, Num 10, pp 1553-1555, issn 0038-1101Article

BiCMOS EDGE detector with correlated-double-sampling readout circuit for pattern recognition neral networkKUO, J. B; CHOU, T. L; WONG, E. J et al.Electronics Letters. 1991, Vol 27, Num 14, pp 1248-1250, issn 0013-5194Article

Two-dimensional transient analysis of a collector-up ECL inverterKUO, J. B; TSEN SHAU YANG; DUTTON, R. W et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 10, pp 1038-1045, issn 0278-0070, 8 p.Article

Closed-form partitioned gate tunneling current model for NMOS devices with an ultra-thin gate oxideLIN, C. H; KUO, J. B.Solid-state electronics. 2009, Vol 53, Num 11, pp 1191-1197, issn 0038-1101, 7 p.Article

Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress EffectSU, V. C; LIN, I. S; KUO, J. B et al.IEEE electron device letters. 2008, Vol 29, Num 6, pp 612-614, issn 0741-3106, 3 p.Article

Partitioned gate tunnelling current model considering distributed effect for CMOS devices with ultra-thin (1nm) gate oxideLIN, C. H; KUO, J. B; SU, K. W et al.Electronics Letters. 2006, Vol 42, Num 3, pp 182-184, issn 0013-5194, 3 p.Article

An analytical velocity overshoot model for 0.1 μm N-channel metal-oxide-silicon devices considering energy transportKUO, J. B; CHANG, Y.-W; CHEN, Y.-G et al.Japanese journal of applied physics. 1996, Vol 35, Num 5A, pp 2573-2577, issn 0021-4922, 1Article

An accurate knee current model considering quasi-saturation for BJTs operating at high current densityCHEN, B. Y; KUO, J. B.Solid-state electronics. 1995, Vol 38, Num 6, pp 1282-1284, issn 0038-1101Article

A BiCMOS dynamic multiplier using Wallace tree reduction architecture and 1.5-V full-swing BiCMOS dynamic logic circuitKUO, J. B; SU, K. W; LOU, J. H et al.IEEE journal of solid-state circuits. 1995, Vol 30, Num 8, pp 950-954, issn 0018-9200Article

An analytical transient model for a 1.5 V BiCMOS dynamic logic circuit for low-voltage deep submicrometer BiCMOS VLSICHIANG, C. S; KUO, J. B.I.E.E.E. transactions on electron devices. 1995, Vol 42, Num 3, pp 549-554, issn 0018-9383Article

A fully analytical partitioned-charge-based model for linearly-graded SiGe-base heterojunction bipolar transistorsKUO, J. B; LU, T. C.Solid-state electronics. 1994, Vol 37, Num 8, pp 1561-1566, issn 0038-1101Article

Closed-form physical model for VLSI bipolar devices considering energy transportKUO, J. B; HUANG, H. J; LU, T. C et al.Electronics Letters. 1994, Vol 30, Num 3, pp 268-269, issn 0013-5194Article

Subthreshold characteristics of a SiGe-channel PMOS device operating at 77 KKUO, J. B; SIM, J. H.Solid-state electronics. 1994, Vol 37, Num 1, pp 204-206, issn 0038-1101Article