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D-flip-flop with a programmable delay with power consumption for implementation in smart sensorsRUTKA, M. J; WOLFFENBUTTEL, R. F.Sensors and actuators. A, Physical. 1993, Vol 37-38, pp 600-606, issn 0924-4247Conference Paper

Speech analysis and synthesis methods developed at ECL in NTT-from LPC to LSPSUGAMURA, N; ITAKURA, F.Speech communication. 1986, Vol 5, Num 2, pp 199-215, issn 0167-6393Article

An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capabilityVAN TRAN, H; SCOTT, D. B; PAK KUEN FUNG et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1041-1047, issn 0018-9200Article

A double-word-line structure in bipolar ECL random access memoryKAYANO, S; ANAMI, K; NAKASE, Y et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 4, pp 543-547, issn 0018-9200Article

Logic array design for 250 MHzOBERMEIER, W.IEEE transactions on industrial electronics (1982). 1986, Vol 33, Num 4, pp 355-360, issn 0278-0046Article

ECL fault modellingMORANDI, C; NICCOLAI, L; FANTINI, F et al.IEE proceedings. Part E. Computers and digital techniques. 1988, Vol 135, Num 6, pp 312-317, issn 0143-7062Article

Formal hadware verification methodology and its application to a network interface chipGORDON, M. J. C; HERBERT, J.IEE proceedings. Part E. Computers and digital techniques. 1986, Vol 133, Num 5, pp 255-270, issn 0143-7062Article

Advances in bipolar VLSIWILSON, G. R.Proceedings of the IEEE. 1990, Vol 78, Num 11, pp 1707-1719, issn 0018-9219Article

Minimisation technique for series-gated emitter-coupled logicCHOY, C. S; JONES, P. L.IEE proceedings. Part G. Electronic circuits and systems. 1989, Vol 136, Num 3, pp 105-113, issn 0143-7089, 9 p.Article

Emission enhancement of electrochemiluminescence device by mixing highly scattering mediumISHIKAWA, T; YAGYU, K; SATO, S et al.Electronics letters. 2009, Vol 45, Num 2, pp 129-130, issn 0013-5194, 2 p.Article

Design and optimization of a low-power and very-high-performance 0.25 μm advanced pnp bipolar processDJEZZAR, B.Microelectronics journal. 1998, Vol 29, Num 1-2, pp 13-19, issn 0959-8324Article

A simple expression for ECL propagation delay including non-quasi-static effectsMCGREGOR, J. M; ROULSTON, D. J; HAMEL, J. S et al.Solid-state electronics. 1993, Vol 36, Num 3, pp 391-396, issn 0038-1101Article

Resistivity control of boron-doped polysilicon resistorsPENNELL, R; FOERSTNER, J.Journal of the Electrochemical Society. 1991, Vol 138, Num 3, pp 860-863, issn 0013-4651, 4 p.Article

On the scaling property of trench isolation capacitance for advanced high-performance ECL circuitsLU, P. F; CHUANG, C. T.I.E.E.E. transactions on electron devices. 1990, Vol 37, Num 10, pp 2270-2274, issn 0018-9383, 5 p.Article

Design for reducing alpha-particle-induced soft errors in ECL logic circuitryOKABE, M; TATSUKI, M; ARIMA, Y et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1397-1403, issn 0018-9200Article

ECL storage elements : Modeling of faulty behaviorMENON, S. M; MALAIYA, Y. K; JAYASUMANA, A. P et al.IEEE transactions on circuits and systems. 2, Analog and digital signal processing. 1997, Vol 44, Num 11, pp 970-974, issn 1057-7130Article

High-speed soft-error-immune ECL circuits with fully isolated transistorsUENO, K.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 695-699, issn 0018-9383Article

A 23-ps/2.1-mW ECL gate with an AC-coupled active pull-down emitter-follower stageKAI-YAP TOH; CHING-TE CHUANG; TZE-CHIANG CHEN et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1301-1306, issn 0018-9200Article

An experimental soft-error-immune 64-kbit 3-ns ECL bipolar RAMYAMAGUCHI, K; NANBU, H; KANETANI, K et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 5, pp 1390-1396, issn 0018-9200Article

Electrogenerated chemiluminescence from single cadmium selenide nanocrystalsJIGANG ZHOU; JUN ZHU; ZHIFENG DING et al.Proceedings - Electrochemical Society. 2005, pp 129-137, issn 0161-6374, isbn 1-56677-462-4, 9 p.Conference Paper

Investigation of the instability of the signal time delay in microcircuit logic elementsADAMOV, Yu. F; MOKEROV, V. G; SHCHELEVA, I. M et al.Journal of communications technology & electronics. 1999, Vol 44, Num 11, pp 1278-1281, issn 1064-2269Article

On the optimisation of outside spacer bipolar transistors for 0.5 μm high performance mixed analog/digital BiCMOSCUTHBERTSON, A; DECOUTERE, S; DEFERM, L et al.Electrical engineering (Berlin). 1996, Vol 79, Num 5, pp 343-351, issn 0948-7921Article

A fully analytical transient model for an ECL inverter using a partitioned-charge-based BJT modelHUANG, H. J; KUO, J. B.I.E.E.E. transactions on electron devices. 1994, Vol 41, Num 5, pp 864-867, issn 0018-9383Article

A low-capacitance bipolar/BiCMOS isolation technology. II: Circuit performance and device self-heatingBURGHARTZ, J. N; CIFUENTES, A. O; WARNOCK, J. D et al.I.E.E.E. transactions on electron devices. 1994, Vol 41, Num 8, pp 1388-1395, issn 0018-9383Article