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Study of model esterifications and of polyesterifications catalyzed by various organometallic derivatives. III. Kinetic and mechanistic study of esterifications catalyzed by tetrabutoxytitanium or zirconiumLEVERD, F; FRADET, A; MARECHAL, E et al.European polymer journal. 1987, Vol 23, Num 9, pp 705-709, issn 0014-3057Article

Amélioration du procédé de fabrication des poly(éther-B-amide)s Pebax = Improving pebac poly(ether-B-amide)s manufacturing processCUZIN, D; ALLEAUME, D; FRADET, A et al.1986, 64 p.Report

Impact of a 10 nm ultra-thin BOX (UTBOX) and ground plane on FDSOI devices for 32 nm node and belowFENOUILLET-BERANGER, C; PERREAU, P; HAENDLER, S et al.Solid-state electronics. 2010, Vol 54, Num 9, pp 849-854, issn 0038-1101, 6 p.Conference Paper

Highly-performant 38nm SON (silicon-on-nothing) P-MOSFETs with 9nm-thick channelsMONFRAY, S; SKOTNICKI, T; HAOND, M et al.IEEE International SOI conference. 2002, pp 20-22, isbn 0-7803-7439-8, 3 p.Conference Paper

New concept of high-k integration in MOSFET's by a deposition through contact holesHARRISON, S; CORONEL, P; WACQUANT, F et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 321-325, issn 0167-9317, 5 p.Conference Paper

230 GHz self-aligned SiGeC HBT for 90 nm BiCMOS technologyCHEVALIER, P; FELLOUS, C; BONNOUVRIER, J et al.Bipolar/BiCMOS Circuits and Technology Meetings. 2004, pp 225-228, isbn 0-7803-8618-3, 1Vol, 4 p.Conference Paper

Poly-gate REplacement through contact hole (PRETCH) : A new method for high-k/metal gate and multi-oxide implementation on chipHARRISON, S; CORONEL, P; BARGE, D et al.International Electron Devices Meeting. 2004, pp 291-294, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

SON (Silicon-On-Nothing) technological CMOS platform : Highly performant devices and SRAM cellsMONFRAY, S; CHANEMOUGAME, D; DESCOMBES, S et al.International Electron Devices Meeting. 2004, pp 635-638, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

Gate-all-around technology: Taking advantage of ballistic transport?HUGUENIN, J. L; BIDAL, G; ORLANDO, B et al.Solid-state electronics. 2010, Vol 54, Num 9, pp 883-889, issn 0038-1101, 7 p.Conference Paper

FDSOI devices with thin BOX and ground plane integration for 32 nm node and belowFENOUILLET-BERANGER, C; DENORME, S; CASSE, M et al.Solid-state electronics. 2009, Vol 53, Num 7, pp 730-734, issn 0038-1101, 5 p.Conference Paper

Folded fully depleted FET using Silicon-On-Nothing technology as a highly W-scaled planar solutionBIDAL, G; LOUBET, N; BARNOLA, S et al.Solid-state electronics. 2009, Vol 53, Num 7, pp 735-740, issn 0038-1101, 6 p.Conference Paper

New metal gate architecture achieved by chemical vapor deposition for a complete tunnel fillREGNIER, C; WACQUANT, F; LEVERD, F et al.Proceedings - Electrochemical Society. 2003, pp 391-396, issn 0161-6374, isbn 1-56677-396-2, 6 p.Conference Paper

High performance 40nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gateTAVEL, B; GARROS, X; LEVERD, F et al.IEDm : international electron devices meeting. 2002, pp 429-432, isbn 0-7803-7462-2, 4 p.Conference Paper

50nm: Gate all around (GAA): Silicon on nothing (SON): Devices: A simple way to co-integration of GAA transistors within bulk MOSFET processMONFRAY, S; SKOTNICKI, T; HAOND, M et al.Symposium on VLSI technology. 2002, pp 108-109, isbn 0-7803-7312-X, 2 p.Conference Paper

SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5nm-thick Si-films: The simplest way to integration of metal gates on thin FD channelsMONFRAY, S; SKOTNICKI, T; LEVERD, F et al.IEDm : international electron devices meeting. 2002, pp 263-266, isbn 0-7803-7462-2, 4 p.Conference Paper

Thin film materials, processes, and reliability (plasma processing for the 100nm node and copper interconnects with low-k inter-level dielectric films)Mathad, G.S; Case, T.S; Leverd, F et al.Proceedings - Electrochemical Society. 2003, issn 0161-6374, isbn 1-56677-393-8, X, 424 p, isbn 1-56677-393-8Conference Proceedings

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