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CIRCUIT ANALYSIS, LOGIC SIMULATION, AND DESIGN VERIFICATION FOR VLSIRUEHLI AE; DITLOW GS.1983; PROCEEDINGS OF THE IEEE; ISSN 0018-9219; USA; DA. 1983; VOL. 71; NO 1; PP. 34-48; BIBL. 109 REF.Article

LOGIC SIMULATION. II.BLUNDEN DF; BOYCE AH; TAYLOR G et al.1977; MARCONI REV.; G.B.; DA. 1977; VOL. 40; NO 207; PP. 236-253; BIBL. 3 REF.Article

THE CASE FOR LOGIC SIMULATION.LAWRENCE B.1976; NEW ELECTRON.; G.B.; DA. 1976; VOL. 9; NO 18; PP. 50-53 (2P.)Article

COMPUTER-AIDED DESIGN OF LSI CIRCUITSNIESSEN C.1977; PHILIPS TECH. REV.; NLD; DA. 1977; VOL. 37; NO 11-12; PP. 278-290; BIBL. 10 REF.Article

LOGICAL VERIFICATION OF MASK PATTERNS BY LOGIC SIMULATIONKAWAMURA M; HIRABAYASHI K.1980; SYSTEMS, COMPUTERS, CONTROLS; ISSN 0096-8765; USA; DA. 1980; VOL. 11; NO 3; PP. 83-89; BIBL. 2 REF.Article

VERFAHRENSWEISE ZUR BEWERTUNG VON GEFAEHDUNGEN BEIM BETREIBEN VON STARKSTROMANLAGEN MIT HILFE MITTELWERTORIENTIERTER RECHENVERFAHREN = METHODE D'ESTIMATION DES RISQUES DANS LES INSTALLATIONS A COURANT FORT A L'AIDE DE METHODES DE CALCUL EN VALEUR MOYENNELANGE P.1980; ELEKTRIE; DDR; DA. 1980; VOL. 34; NO 4; PP. 183-185; ABS. RUS/ENG; BIBL. 3 REF.Article

DETECTING RACES WITH A PRODUCTION ENVIRONMENT LOGIC SIMULATORACCAMPO P.1977; I.E.E.E. TRANS. MANUFG TECHNOL.; USA; DA. 1977; PP. 40-46; BIBL. 1 REF.Article

SIMULATION LOGIQUE DES GRANDS CIRCUITS INTEGRES EN LANGAGE ALGORITHMIQUE FORTRANVOLKOGON VP; KORNEJCHUK VI; MOLCHANOV AA et al.1976; IZVEST. VYSSH. UCHEBN. ZAVED., RADIOELEKTRON.; S.S.S.R.; DA. 1976; VOL. 19; NO 6; PP. 44-50; BIBL. 4 REF.Article

MODELLE DER BRAND- UND EXPLOSIONSGEFAEHRDUNG ELEKTROTECHNISCHER ANLAGEN = MODELES DE RISQUE D'INCENDIE ET D'EXPLOSION DANS LES INSTALLATIONS ELECTRIQUESSISKOV VS.1980; ELEKTRIE; DDR; DA. 1980; VOL. 34; NO 4; PP. 177-179; ABS. RUS/ENG; BIBL. 1 REF.Article

LOGIC SIMULATION. I.BLUNDEN DF; BOYCE AH; TAYLOR G et al.1977; MARCONI REV.; G.B.; DA. 1977; VOL. 40; NO 206; PP. 157-171; BIBL. 11 REF.Article

LOMACH: A MOS CIRCUIT MASK CHECKING LOGIC SIMULATORSZANTO L.1982; COMPUTER-AIDED DESIGN; ISSN 0010-4485; GBR; DA. 1982; VOL. 14; NO 6; PP. 313-319; BIBL. 7 REF.Article

VISTA: A VLSI CAD SYSTEMDASEKING HW; GARDNER RI; WEIL PB et al.1982; IEEE TRANS. COMPUT. AIDED DES. INTEGR. CIRCUITS SYST.; USA; DA. 1982; VOL. 1; NO 1; PP. 36-52; BIBL. 56 REF.Article

FUNKTIONSORIENTIERTE BERECHNUNG DER EINTRITTSWAHRSCHEINLICHKEIT VON ARBEITSUNFAELLEN AUS FEHLERBAEUMEN = CALCUL FONCTIONNEL DES PROBABILITES D'ACCIDENTS DU TRAVAIL A PARTIR DES ARBRES DE DEFAUTUHLIG D.1980; ELEKTRIE; DDR; DA. 1980; VOL. 34; NO 4; PP. 196-198; ABS. RUS/ENG; BIBL. 5 REF.Article

MACLOS-MASK CHECKING LOGIC SIMULATORHIRABAYASHI K; KAWAMURA M.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 3; PP. 368-370; BIBL. 1 REF.Article

LOGIC SIMULATION USING INTERACTIVE HARDWARE.TONG LC; GOURLEY SF.1977; COMPUTER AIDED DESIGN; G.B.; DA. 1977; VOL. 9; NO 2; PP. 99-102; BIBL. 6 REF.Article

Accurate logic simulation by overcoming the unknown value propagation problemKANG, Sungho; SZYGENDA, Stephen A.Simulation (San Diego, Calif.). 2003, Vol 79, Num 2, pp 59-68, issn 0037-5497, 10 p.Article

THEORETICAL CONSIDERATION OF THE DIGITAL SIMULATION CONTAINING UNKNOWN STATESKANADA H.1977; SYST. COMPUTERS CONTROLS; USA; DA. 1977 PUBL. 1978; VOL. 8; NO 1; PP. 9-16; BIBL. 9 REF.Article

A LANGUAGE FOR MODELING THE FUNCTIONAL AND TIMING CHARACTERISTICS OF COMPLEX DIGITAL COMPONENTS FOR LOGIC SIMULATIONSCHULER DM.1979; INTERNATIONAL SYMPOSIUM ON COMPUTER HARDWARE DESCRIPTION LANGUAGES. 4/1979/PALO ALTO CA; USA; NEW YORK: IEEE; DA. 1979; PP. 54-59; BIBL. 11 REF.Conference Paper

A LOGICAL MODEL FOR THE REMOTE CONTROL OF POWER SYSTEM TOPOLOGYPARTHASARATHY S; DESCHIZEAUX P.1979; MATH. COMPUTERS SIMUL; NLD; DA. 1979; VOL. 21; PP. 221-225; BIBL. 4 REF.Article

DIGITAL TESTING: THE ECONOMICS OF LOGIC SIMULATION.ACCAMPO PW.1977; ELECTRON. PACKAG. PRODUCT.; U.S.A.; DA. 1977; VOL. 17; NO 9 PART. 2; PP. T14-T21; BIBL. 1 REF.Article

A COMPUTER ARCHITECTURE FOR DIGITAL LOGIC SIMULATIONBARTO R; SZYGENDA SA.1980; ELECTRON. ENG.; ISSN 0013-4902; GBR; DA. 1980; VOL. 52; NO 642; PP. 35-66; 11 P.Article

LOGICHESKIE PROBLEMY SISTEMNOGO ANALIZA TRUDOVYKH RESURSOV. MODELIROVANIE I FORMALIZATSIYA. = PROBLEMES LOGIQUES D'ANALYSE DE SYSTEME DES RESSOURCES HUMAINES. SIMULATION ET FORMALISATIONLADENKO IS; ZVONOV EN.1975; NOVOSIBIRSK; NAUKA; DA. 1975; PP. 1-237; BIBL. 9 P.Book

FAULT MODELING AND LOGIC SIMULATION OF CMOS AND MOS INTEGRATED CIRCUITSWADSACK RL.1978; BELL SYST. TECH. J.; USA; DA. 1978; VOL. 57; NO 5; PP. 1449-1474; BIBL. 7 REF.Article

TIME-OUT: A GRAPHIC OUTPUT PACKAGE FOR A LOGIC SIMULATORFLEMING MA; COX GW; CARROLL BD et al.1978; SOUTHEASTCON '78. INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS. REGION 3. CONFERENCE/1978-04-10/ATLANTA GA; USA; NEW YORK: IEEE; DA. 1978; 300-302; BIBL. 1 REF.Conference Paper

FAULT COVERAGE IN DIGITAL INTEGRATED CIRCUITSWADSACK RL.1978; BELL SYST. TECH. J.; USA; DA. 1978; VOL. 57; NO 5; PP. 1475-1488; BIBL. 7 REF.Article

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