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Results 1 to 25 of 6464

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High performance bipolar FPLAsTAKEDA, T; MATSUHIRO, K; SUZUKI, M et al.Review of the electrical communication laboratories. 1983, Vol 31, Num 4, pp 566-575, issn 0029-067XArticle

IUMRS-ICEM-2010. Materials and Devices for Future Logic TechnologyCHOI, Rino; CHEOL SEONG HWANG; YOUNG-BAE PARK et al.Microelectronic engineering. 2012, Vol 89, issn 0167-9317, 143 p.Conference Proceedings

Multi-valued logic systemsHAWKEN, R. E.International journal of electronics. 1989, Vol 67, Num 5, issn 0020-7217, 142 p.Serial Issue

Application of AlGaAs/GaAs HBT's to high-speed CML logic family fabricationMOHAMMAD MADIHIAN; TANAKA, S.-I; HAYAMA, N et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 4, pp 625-631, issn 0018-9383, 7 p.Article

On the approach of the stationary state in Kauffman's random Boolean networkHILHORST, H. J; NIJMEIJER, M.Journal de physique (Paris). 1987, Vol 48, Num 2, pp 185-191, issn 0302-0738Article

Sur la vérification complète des matrices logiques programmables. INOVIKOV, YA. A.Avtomatika i telemehanika. 1984, Num 6, pp 146-153, issn 0005-2310Article

Variable threshold logic ― a highly flexible logicKIM, C; KUSHIYAMA, N; SHONO, K et al.IEEE electron device letters. 1985, Vol 6, Num 7, pp 390-393, issn 0741-3106Article

Eléments logiques pour les systèmes à structure variableGOLIK, L. L; ELINSON, M. I; PEROV, N. I et al.Mikroèlektronika (Moskva). 1984, Vol 13, Num 3, pp 206-213, issn 0544-1269Article

Modélisation de circuits logiques élémentaires à effet Josephson = Modelling of elementary logic Josephson effect circuitsMATHERON, G; MAS, P; MIGNY, P et al.1982, 43 p.Report

Multilevel logical networksKARPOVSKY, M.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 215-226, issn 0018-9340Article

An algorithm for the partitioning of logic circuitsROBERTS, M. W; LALA, P. K.IEE proceedings. Part E. Computers and digital techniques. 1984, Vol 131, Num 4, pp 113-118, issn 0143-7062Article

Hard magnetic cylindrical domains (HMD) as elements of multistate logicSZKODNY, T.Bulletin of the Polish Academy of Sciences. Technical sciences. 1984, Vol 32, Num 5-6, pp 333-339, issn 0239-7528Article

ATILA, a program to generate test patterns for scan testable logicSMITH, P. J.GEC journal of research. 1988, Vol 6, Num 3, pp 147-151, issn 0264-9187Article

Development of a user friendly gate-level logic simulatorSTIGALL, P. D; KUMAR SHIV.Computers & electrical engineering. 1987, Vol 13, Num 3-4, pp 147-167, issn 0045-7906Article

Evaluating the signal-reliability of logic circuitsKYUNG-SHIK KOH.IEEE transactions on reliability. 1985, Vol 34, Num 3, pp 233-235, issn 0018-9529Article

Optimal shut-down logic for protective systemsKOHDA, T; KUMAMOTO, H; INOUE, K et al.IEEE transactions on reliability. 1983, Vol 32, Num 1, pp 26-29, issn 0018-9529Article

Hybrid integratorKAWABE, S; OHNIWA, K.Electrical engineering in Japan. 1983, Vol 103, Num 6, pp 134-140, issn 0424-7760Article

Einsatzerfahrungen und Weiterentwicklung des Gate-Array-Entwurfssystems PC-GAD = Experiences obtained and future development of the gate assay design system PC-GADPAULIUK, J.Wissenschaftliche Zeitschrift der Technischen Universität Karl-Marx-Stadt. 1989, Vol 31, Num 4, pp 521-527, issn 0863-0615, 7 p.Article

Switching in NERFET circuitsKASTALSKY, A; LURYI, S; GOSSARD, A. C et al.IEEE electron device letters. 1985, Vol 6, Num 7, pp 347-349, issn 0741-3106Article

Iterative exhaustive pattern generation for logic testingTANG, D. T; CHEN, C. L.IBM journal of research and development. 1984, Vol 28, Num 2, pp 212-219, issn 0018-8646Article

A method for generating weighted random test patternsWAICUKAUSKI, J. A; LINDBLOOM, E; EICHELBERGER, E. B et al.IBM journal of research and development. 1989, Vol 33, Num 2, pp 149-161, issn 0018-8646, 13 p.Article

Parity predictor for shifting-output addersVASSILIADIS, S; PUTRINO, M; SCHWARZ, E. M et al.Electronics Letters. 1989, Vol 25, Num 6, pp 422-424, issn 0013-5194, 3 p.Article

Error-sevure and error-propagating concepts for strongly fault-secure systemsNANYA, T; KAWAMURA, T.Systems and computers in Japan. 1987, Vol 18, Num 3, pp 11-18, issn 0882-1666Article

Fine Entwurfsstrategie für den logischen Schaltungsentwurf = Une stratégie pour le dessin logique des circuits = A strategy for the logical design of circuitsBOCHMANN, D; POSTHOFF, C.Wissenschaftliche Zeitschrift der Technischen Hochschule Karl-Marx-Stadt. 1984, Vol 25, Num 6, pp 805-813, issn 0372-7610Article

Properties of wired logicKAMBAYASHI, Y; MUROGA, S.IEEE transactions on computers. 1986, Vol 35, Num 6, pp 550-563, issn 0018-9340Article

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