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Charge redistribution and noise margins in domino CMOS logicPRETORIUS, J. A; SHUBAT, A. S; SALAMA, C. A. T et al.IEEE transactions on circuits and systems. 1986, Vol 33, Num 8, pp 786-793, issn 0098-4094Article

Testing of multiple-output domino logic (MODL) CMOS circuitsJHA, N. K; QIAO TONG.IEEE journal of solid-state circuits. 1990, Vol 25, Num 3, pp 800-805, issn 0018-9200, 6 p.Article

New domino logic precharged by clock and dataYUAN, J.-R; SVENSSON, C; LARSSON, P et al.Electronics Letters. 1993, Vol 29, Num 25, pp 2188-2189, issn 0013-5194Article

Analysis and design optimization of domino CMOS logic with application to standard cellsPRETORIUS, J. A; SHUBAT, A. S; SALAMA, C. A. T et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 2, pp 523-530, issn 0018-9200Article

Noise constrained transistor sizing and power optimization for dual Vt domino logicJUNG, Seong-Ook; KIM, Ki-Wook; KANG, Sung-Mo et al.IEEE transactions on very large scale integration (VLSI) systems. 2002, Vol 10, Num 5, pp 532-541, issn 1063-8210, 10 p.Article

Domino CMOS SCD/SFS 2-out-of-3 and 1-out-of-3 code checkersHANIOTAKIS, Th; TSIATOUHAS, Y; EFSTATHIOU, C et al.International journal of electronics. 2003, Vol 90, Num 2, pp 145-158, issn 0020-7217, 14 p.Article

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