A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applicationsMORISHITA, Fukashi; HAYASHI, Isamu; SHINKAWATA, Hiroki et al.IEEE International Solid-State Circuits Conference. 2004, pp 202-203, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

An 800MHz embedded DRAM with a concurrent refresh modeKIRIHATA, Toshiaki; PARRIES, Paul; WORDEMAN, Matt et al.IEEE International Solid-State Circuits Conference. 2004, pp 206-207, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Architecture and circuit techniques for a reconfigurable memory blockKEN MAI; HO, Ron; ALON, Elad et al.IEEE International Solid-State Circuits Conference. 2004, pp 500-501, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

At-speed interconnect test and diagnosis of external memories on a systemKIM, Heon C; JUN, Hong-Shin; XINLI GU et al.International Test Conference. 2004, pp 156-162, isbn 0-7803-8580-2, 1Vol, 7 p.Conference Paper

Low-temperature operation of silicon dynamic random-access memoriesWYNS, P; ANDERSON, R. L.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1423-1428, issn 0018-9383, 6 p.Article

Dual-ported memorySCAYSBROOK, F. F.Review of scientific instruments. 1986, Vol 57, Num 1, pp 122-123, issn 0034-6748Article

Interfacing multi-processors using devices with dual-port RAMGONZALES, D. R.Microelectronics. 1985, Vol 16, Num 3, pp 5-12, issn 0026-2692Article

All points addressable raster display memoryMATICK, R; LING, D. T; GUPTA, S et al.IBM journal of research and development. 1984, Vol 28, Num 4, pp 379-392, issn 0018-8646Article

Mainstream memory technologies in deep submicronNATARAJAN, Sreedhar; ALVANDPOUR, Atila.Mediterranean electrotechnical conference. 2004, isbn 0-7803-8271-4, 3Vol, Vol.1, 175-178Conference Paper

A 130nm 1.1V 143MHz SRAM-like. Embedded DRAM COMPILER with dual asymmetric bit line sensing scheme and quiet unselected IO schemeNOH, K. J; CHOI, Y. J; JOO, J. D et al.Symposium on VLSI Circuits. 2003, pp 190-191, isbn 0-7803-8287-0, 1Vol, 2 p.Conference Paper

On the design of hybrid DRAM/SRAM memory schemes for fast packet buffersGARCIA, Jorge; MARCH, Maribel; CERDA, Llorenc et al.Workshop on high performance switching and routing. 2004, pp 15-19, isbn 0-7803-8375-3, 1Vol, 5 p.Conference Paper

Per-bit sense amplifier scheme for 1GHz SRAM macro in sub-100nm CMOS technologyTAKEDA, K; HAGIHARA, Y; AIMOTO, Y et al.IEEE International Solid-State Circuits Conference. 2004, pp 502-503, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 4Gb/s/pin 4-level simultaneous bidirectional 10 using a 500MHz clock for high-speed memoryKIM, Jin-Hyun; KIM, Su-A; KIM, Woo-Seop et al.IEEE International Solid-State Circuits Conference. 2004, pp 248-249, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A new vertically stacked poly-Si MOSFET for 533MHz high speed 64Mbit SRAMKIKUCHI, T; MORIYA, S; NAKATSUKA, Y et al.International Electron Devices Meeting. 2004, pp 923-926, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper

An alpha immune and ultra low neutron SER high density SRAMROCHE, Philippe; JACQUET, Francois; CAILLAT, Christian et al.IEEE international reliability physics symposium. 2004, pp 671-672, isbn 0-7803-8315-X, 1Vol, 2 p.Conference Paper

The effectiveness of scan test and its new variantsVAN DE GOOR, Ad J; HAMDIOUI, Said; AL-ARS, Zaid et al.IEEE International Workshop on Memory Technology, Design and Testing. 2004, pp 26-31, isbn 0-7695-2193-2, 1Vol, 6 p.Conference Paper

Statistical approach to design DRAM bitcell considering overlay errorsPYO, Yu-Jin; KIM, Dae-Wook; PARK, Jai-Kyun et al.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7275, issn 0277-786X, isbn 978-0-8194-7528-2 0-8194-7528-9, 1Vol, 72751L.1-72751L.7Conference Paper

Comparison between neutron-induced system-SER and accelerated-SER in SRAMsKOBAYASHI, Hajime; USUKI, Hideki; SHIRAISHI, Ken et al.IEEE international reliability physics symposium. 2004, pp 288-293, isbn 0-7803-8315-X, 1Vol, 6 p.Conference Paper

Exploring the limits of high temperature thermal processing for advanced 8-inch power technology manufacturingRUPP, T; DYROFF, N; SORSCHAG, K et al.IEEE / SEMI advanced semiconductor manufacturing conference. 2004, pp 27-31, isbn 0-7803-8312-5, 1Vol, 5 p.Conference Paper

Testing of inter-word coupling faults in word-oriented SRAMsWANG, X; OTTAVI, M; LOMBARDI, F et al.IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 2004, pp 111-119, isbn 0-7695-2241-6, 1Vol, 9 p.Conference Paper

A 0.9ns random cycle 36Mb network SRAM with 33mW standby powerPILO, Harold; BRACERAS, Geordie; HALL, Stu et al.Symposium on VLSI Circuits. 2003, pp 284-287, isbn 0-7803-8287-0, 1Vol, 4 p.Conference Paper

Global pattern density control by resizing fill patterns for CD skew compensationSHIN, Jae-Pil; CHOI, Jin-Sook; PARK, Sung-Gyu et al.Proceedings of SPIE, the International Society for Optical Engineering. 2006, issn 0277-786X, isbn 0-8194-6358-2, vol 2, 628339.1-628339.6Conference Paper

A 600MHZ DSP with 24Mb embedded DRAM with an enhanced instruction set for wireless communicationADELMAN, Yehuda; AGUR, Dana; MEIROV, Henri et al.IEEE International Solid-State Circuits Conference. 2004, pp 418-419, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 300MHz 25μA/Mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage-active mode for mobile-phone application processorYAMAOKA, Masanao; SHINOZAKI, Yoshihiro; MAEDA, Noriaki et al.IEEE International Solid-State Circuits Conference. 2004, pp 494-495, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Low power bank-based multi-port SRAM design due to bank standby modeZHAOMIN ZHU; JOHGUCHI, Koh; MATTAUSCH, Hans Jürgen et al.MWSCAS : Midwest symposium on circuits and systems. 2004, isbn 0-7803-8346-X, 3Vol, Vol I, 569-572Conference Paper