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An 18-ns 1-Mbit CMOS SRAMSHIMADA, H; TANGE, Y; TANIMOTO, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1073-1077, issn 0018-9200Article

Design consideration of a static memory cellANAMI, K; YOSHIMOTO, M; SHINOHARA, H et al.IEEE journal of solid-state circuits. 1983, Vol 18, Num 4, pp 414-418, issn 0018-9200Article

A 12-ns ECL I/O 256K×1-bit SRAM using a 1-υm BiCMOS technologyKERTIS, R. A; SMITH, D. D; BOWMAN, T. L et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1048-1053, issn 0018-9200Article

A 14-ns 1-Mbit CMOS SRAM with variable bit organizationKOHNO, Y; WADA, T; ANAMI, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1060-1066, issn 0018-9200Article

A 25-ns low-power full-CMOS 1-Mbit (128K×8) SRAMCHU, S. T; DIKKEN, J; HARTGRING, C. D et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1078-1084, issn 0018-9200Article

A 4-ns 4K×1-bit two-port BiCMOS SRAMTSEN-SHAU YANG; HOROWITZ, M. A; WOOLEY, B. A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1030-1040, issn 0018-9200Article

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devicesWONG, D. T; ADAMS, R. D; ARUP BHATTACHARYYA et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1095-1103, issn 0018-9200Article

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A 25 ns 64 K static RAMYAMANAKA, T; KOSHIMARU, S; KUDOH, O et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 572-577, issn 0018-9200Article

GaAs 1kb static RAM fabrication technologyASAI, K; OWADA, K; KURUMADA, K et al.Review of the electrical communication laboratories. 1985, Vol 33, Num 1, pp 115-121, issn 0029-067XArticle

Process and performance comparison of an 8K×8-bit SRAM in three stacked CMOS technologiesHITE, L. R; SUNDARESAN, R; MALHI, S. D. S et al.IEEE electron device letters. 1985, Vol 6, Num 10, pp 548-550, issn 0741-3106Article

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A 20 ns 64 K CMOS static RAMMINATO, O; MASUHARA, T; SASAKI, T et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 6, pp 1008-1013, issn 0018-9200Article

A divided word-line structure in the static RAM and its application to a 64 K full CMOS RAMYOSHIMOTO, M; ANAMI, K; SHINOHARA, H et al.IEEE journal of solid-state circuits. 1983, Vol 18, Num 5, pp 479-485, issn 0018-9200Article

A 64K SRAM with high immunity from heavy ion induced latch-upSHIONO, N; SAKAGAWA, Y; MATSUMOTO, T et al.IEEE electron device letters. 1986, Vol 7, Num 1, pp 20-22, issn 0741-3106Article

A high performance 256K (512K) static ROMFONG, E; CHANG, J; WEN PERNG TAI et al.IEEE journal of solid-state circuits. 1983, Vol 18, Num 6, pp 807-810, issn 0018-9200Article

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