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SILICON-ON-SAPPHIRE SUBSTRATES OVERCOME MOS LIMITATIONSRAPP AK; ROSS EC.1972; ELECTRONICS; U.S.A.; DA. 1972; VOL. 45; NO 20; PP. 113-116Serial Issue

DEPLETION M.O.S. POWER TRANSISTORS.FARZAN B; SALAMA CAT.1975; ELECTRON. LETTERS; G.B.; DA. 1975; VOL. 11; NO 23; PP. 565-566; BIBL. 6 REF.Article

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N-CHANNEL ION-IMPLANTED ENHANCEMENT*DEPLETION FET CIRCUIT AND FABRICATION TECHNOLOGYFORBES L.1973; I.E.E.E. J. SOLID-STATE CIRCUITS; U.S.A.; DA. 1973; VOL. 8; NO 3; PP. 226-230; BIBL. 6 REF.Serial Issue

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COMPUTERGERECHTE MODELLFAMILIE FUER INTEGRIERTE MOS-TRANSISTOREN. II: VERARMUNGSTRANSISTOR, CMOS-TECHNIK = FAMILLE DE MODELES CONVENANT A LA SIMULATION SUR ORDINATEUR DE TRANSISTORS MOS INTEGRES. DEUXIEME PARTIE: TRANSISTOR A APPAUVRISSEMENT EN TECHNOLOGIE MOS COMPLEMENTAIREDIENER KH; FISCHER P; GAERTNER U et al.1980; NACHR.-TECH., ELEKTRON.; DDR; DA. 1980; VOL. 30; NO 4; PP. 155-158; ABS. RUS/ENG/FRE; BIBL. 11 REF.Article

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C-V CHARACTERISTICS OF ION IMPLANTED DEPLETION IGFETS AND BURIED CHANNEL CCDS.TAYLOR GW.1976; SOLID-STATE ELECTRON.; G.B.; DA. 1976; VOL. 19; NO 6; PP. 495-503; BIBL. 11 REF.Article

MODELING OF AN ION-IMPLANTED SILICON-GATE DEPLETION-MODE IGF ET.HUANG JST; TAYLOR GW.1975; I.E.E.E. TRANS. ELECTRON. DEVICES; U.S.A.; DA. 1975; VOL. 22; NO 11; PP. 995-1001; BIBL. 5 REF.Article

SOME USEFUL SIGNAL PROCESSING CIRCUITS USING FETS AND OPERATIONAL AMPLIFIERS1972; MICROELECTRONICS; G.B.; DA. 1972; VOL. 4; NO 3; PP. 44-47Serial Issue

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MANUFACTURING TOLERANCE OF CAPACITOR COUPLED GAAS FET LOGIC CIRCUITSLIVINGSTONE AW; WELBOURN AD; BLAU GL et al.1982; ELECTRON DEVICE LETT.; ISSN 0193-8576; USA; DA. 1982; VOL. 3; NO 10; PP. 284-286; BIBL. 2 REF.Article

A GIGABIT MOS LOGIC CIRCUIT WITH BURIED CHANNEL MOSFET'SNISHIUCHI K; SHIBAYAMA H; NAKAMURA T et al.1980; IEEE J. SOLID-STATE CIRCUITS; ISSN 0018-9200; USA; DA. 1980; VOL. 15; NO 5; PP. 809-816; BIBL. 10 REF.Article

SIMPLE ANALYTICAL MODELS FOR THE TEMPERATURE DEPENDENT THRESHOLD BEHAVIOR OF DEPLETION-MODE DEVICESJAEGER RC; GAENSSLEN FH.1979; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1979; VOL. 14; NO 2; PP. 423-430; BIBL. 19 REF.Article

A SIMPLIFIED SELF-ALIGNED AL-GATE MOS TECHNOLOGY FOR HIGH PERFORMANCE DEPLETION-LOGIC CIRCUITSPEREIRA DE SOUZA J; CHARRY E.1979; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1979; VOL. 14; NO 3; PP. 651-653; BIBL. 7 REF.Article

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PROPAGATION DELAY TIME AND DELAY-POWER PRODUCT OF A SMALL-SIZED DSA-ED GATE CIRCUITHAYASHI Y.1978; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1978; VOL. 13; NO 5; PP. 726-728; BIBL. 4 REF.Article