au.\*:("MORAND, Y")
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Gate-last integration on planar FDSOI for low-VTp and low-EOT MOSFETsMORVAN, S; ANDRIEU, F; ROURE, M.-C et al.Microelectronic engineering. 2013, Vol 109, pp 306-309, issn 0167-9317, 4 p.Article
Highly-performant 38nm SON (silicon-on-nothing) P-MOSFETs with 9nm-thick channelsMONFRAY, S; SKOTNICKI, T; HAOND, M et al.IEEE International SOI conference. 2002, pp 20-22, isbn 0-7803-7439-8, 3 p.Conference Paper
Effect of tungsten chemical vapor deposition nucleation step on via performanceULMER, L; GEORGES, L; VELER, J. C et al.Microelectronic engineering. 1997, Vol 33, Num 1-4, pp 121-127, issn 0167-9317Conference Paper
Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High-κ Dielectrics, and Metallic Source/DrainVINET, M; POIROUX, T; BAUD, L et al.IEEE electron device letters. 2009, Vol 30, Num 7, pp 748-750, issn 0741-3106, 3 p.Article
Bonded planar double-metal-gate NMOS transistors down to 10 nmVINET, M; POIROUX, T; ALLAIN, F et al.IEEE electron device letters. 2005, Vol 26, Num 5, pp 317-319, issn 0741-3106, 3 p.Article
Optimized nickel silicide process formation for high performance sub-65nm CMOS nodesFROMENT, B; CARRON, V; MORAND, Y et al.Proceedings - Electrochemical Society. 2004, pp 191-201, issn 0161-6374, isbn 1-56677-406-3, 11 p.Conference Paper
SON (Silicon-On-Nothing) technological CMOS platform : Highly performant devices and SRAM cellsMONFRAY, S; CHANEMOUGAME, D; DESCOMBES, S et al.International Electron Devices Meeting. 2004, pp 635-638, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper
Characterization of TiSi2 Ohmic and Schottky contacts formed by rapid thermal annealing technologyMALLARDEAU, C; MORAND, Y; ABONNEAU, E et al.Journal of the Electrochemical Society. 1989, Vol 136, Num 1, pp 238-241, issn 0013-4651, 4 p.Article
Ultrathin (5 nm) SiGe-On-Insulator with high compressive strain (-2 GPa): From fabrication (Ge enrichment process) to in-depth characterizationsGLOWACKI, F; LE ROYER, C; GOURHANT, O et al.Solid-state electronics. 2014, Vol 97, pp 82-87, issn 0038-1101, 6 p.Article
The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?VINCENT, B; DAMLENCOURT, J. F; CAMPIDELLI, Y et al.Materials science in semiconductor processing. 2008, Vol 11, Num 5-6, pp 205-213, issn 1369-8001, 9 p.Conference Paper
Work function tuning through dopant scanning and related effects in Ni fully silicided gate for sub-45nm nodes CMOSAIME, D; FROMENT, B; LAVIRON, C et al.International Electron Devices Meeting. 2004, pp 87-90, isbn 0-7803-8684-1, 1Vol, 4 p.Conference Paper
High performance 40nm nMOSFETs with HfO2 gate dielectric and polysilicon damascene gateTAVEL, B; GARROS, X; LEVERD, F et al.IEDm : international electron devices meeting. 2002, pp 429-432, isbn 0-7803-7462-2, 4 p.Conference Paper
50nm: Gate all around (GAA): Silicon on nothing (SON): Devices: A simple way to co-integration of GAA transistors within bulk MOSFET processMONFRAY, S; SKOTNICKI, T; HAOND, M et al.Symposium on VLSI technology. 2002, pp 108-109, isbn 0-7803-7312-X, 2 p.Conference Paper
SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) polysilicon on 5nm-thick Si-films: The simplest way to integration of metal gates on thin FD channelsMONFRAY, S; SKOTNICKI, T; LEVERD, F et al.IEDm : international electron devices meeting. 2002, pp 263-266, isbn 0-7803-7462-2, 4 p.Conference Paper
Fabrication, structural and electrical properties of (110) localized silicon-on-insulator devicesDESTEFANIS, V; HARTMANN, J. M; MONFRAY, S et al.Semiconductor science and technology. 2010, Vol 25, Num 4, issn 0268-1242, 045014.1-045014.10Article
Wideband frequency and in situ characterization of ultra thin ZrO2 and HfO2 films for integrated MIM capacitorsBERTAUD, T; BERMOND, C; LACREVAZ, T et al.Microelectronic engineering. 2010, Vol 87, Num 3, pp 301-305, issn 0167-9317, 5 p.Conference Paper
In situ microwave characterisation of medium-k HfO2 and high-k SrTiO3 dielectrics for metal-insulator-metal capacitors integrated in back-end of line of integrated circuitsVO, T. T; LACREVAZ, T; DEFAY, E et al.IET microwaves, antennas & propagation (Print). 2008, Vol 2, Num 8, pp 781-788, issn 1751-8725, 8 p.Conference Paper
Strain characterization of strained silicon on insulator wafersPAILLARD, V; GHYSELEN, B; POCAS, S et al.Microelectronic engineering. 2004, Vol 72, Num 1-4, pp 367-373, issn 0167-9317, 7 p.Conference Paper
Hybrid deep UV-e-beam lithography for the fabrication of dual damascene structuresMOLLARD, L; TEDESCO, S; DAL'ZOTTO, B et al.Microelectronic engineering. 2001, Vol 57-58, pp 269-275, issn 0167-9317Conference Paper
Copper-silk integration in a 0.18μm double level metal interconnectDEMOLLIENS, O; BERRUYER, P; LOUIS, D et al.IEEE 1999 international interconnect technology conference. 1999, pp 198-199, isbn 0-7803-5174-6Conference Paper
Electromigration failure modes in damascene copper interconnectsARNAUD, L; GONELLA, R; TARTAVEL, G et al.Microelectronics and reliability. 1998, Vol 38, Num 6-8, pp 1029-1034, issn 0026-2714Conference Paper
Control of landscape diversity by catastrophic disturbance: a theory and a case study of fire in a Canadian boreal forestSUFFLING, R; LIHOU, C; MORAND, Y et al.Environmental management (New York, NY). 1988, Vol 12, Num 1, pp 73-78, issn 0364-152XArticle