Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("MOSFET")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Language

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 4760

  • Page / 191
Export

Selection :

  • and

Silicon-on-Nothing MOSFETs : An efficient solution for parasitic substrate coupling suppression in SOI devicesKILCHYTSKA, V; FLANDRE, D; RASKIN, J.-P et al.Applied surface science. 2008, Vol 254, Num 19, pp 6168-6173, issn 0169-4332, 6 p.Conference Paper

A new vertical MOSFET Vertical Logic Circuit (VLC) MOSFET suppressing asymmetric characteristics and realizing an ultra compact and robust logic circuitSAKUI, Koji; ENDOH, Tetsuo.Solid-state electronics. 2010, Vol 54, Num 11, pp 1457-1462, issn 0038-1101, 6 p.Article

A novel surface passivation process for HfO2 Ge MOSFETsNAN WU; QINGCHUN ZHANG; CHUNXIANG ZHU et al.DRC : Device research conference. 2004, pp 19-20, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

Interface control of high-κ gate dielectrics on GeCAYMAX, M; HOUSSA, M; POURTOIS, G et al.Applied surface science. 2008, Vol 254, Num 19, pp 6094-6099, issn 0169-4332, 6 p.Conference Paper

Validation of MOSFET model source-drain symmetryMCANDREW, Colin C.I.E.E.E. transactions on electron devices. 2006, Vol 53, Num 9, pp 2202-2206, issn 0018-9383, 5 p.Article

Reduced self-heating by strained silicon substrate engineeringO'NEILL, A; AGAIBY, R; VERHEYEN, P et al.Applied surface science. 2008, Vol 254, Num 19, pp 6182-6185, issn 0169-4332, 4 p.Conference Paper

Gate-extension overlap control by sb tilt implantation : Fundamentals and applications of advanced semiconductor devicesSHIBAHARA, Kentaro; MAEDA, Nobuhide.IEICE transactions on electronics. 2007, Vol 90, Num 5, pp 973-977, issn 0916-8524, 5 p.Article

Mobility enhancement in strained Si NMOSFETs with HfO2 gate dielectricsRIM, K; GUSEV, E. P; LEE, B. H et al.Symposium on VLSI technology. 2002, pp 12-13, isbn 0-7803-7312-X, 2 p.Conference Paper

A Compact Space and Efficient Drain Current Design for Multipillar Vertical MOSFETsSAKUI, Koji; ENDOH, Tetsuo.I.E.E.E. transactions on electron devices. 2010, Vol 57, Num 8, pp 1768-1773, issn 0018-9383, 6 p.Article

Investigating the effects of the interface defects on the gate leakage current in MOSFETsMAO, Ling-Feng.Applied surface science. 2008, Vol 254, Num 20, pp 6628-6632, issn 0169-4332, 5 p.Article

On the parasitic gate capacitance of small-geometry MOSFETsJAGADESH KUMAR, M; VENKATARAMAN, Vivek; SUMEET KUMAR GUPTA et al.I.E.E.E. transactions on electron devices. 2005, Vol 52, Num 7, pp 1676-1677, issn 0018-9383, 2 p.Article

Exploring the effect of width on performance enhancement in NMOSFETs with a silicon-carbon alloy stressor and a tensile stress silicon nitride linerSHU TONG CHANG; WANG, Wei-Ching; HUANG, Jacky et al.Applied surface science. 2008, Vol 254, Num 19, pp 6177-6181, issn 0169-4332, 5 p.Conference Paper

Fabrication of Ge-channel MOSFETs by using replacement gate process and selective epitaxial growthTERASHIMA, Koichi; TANABE, Akihito; NAKAGAWA, Takashi et al.Applied surface science. 2008, Vol 254, Num 19, pp 6165-6167, issn 0169-4332, 3 p.Conference Paper

Source/drain engineering for MOSFETs with embedded-Si:C technologyITOKAWA, Hiroshi; YASUTAKE, Nobuaki; KUSUNOKI, Naoki et al.Applied surface science. 2008, Vol 254, Num 19, pp 6135-6139, issn 0169-4332, 5 p.Conference Paper

A compact and accurate MOSFET model with simple expressions for linear, saturation and sub-threshold regionsKATTO, Hisao.Solid-state electronics. 2006, Vol 50, Num 3, pp 301-308, issn 0038-1101, 8 p.Article

Comments on: Modeling MOSFET surface capacitance behavior under non-equilibriumJIN HE; XING ZHANG; YANGYUAN WANG et al.Solid-state electronics. 2006, Vol 50, Num 2, pp 259-262, issn 0038-1101, 4 p.Article

A novel surface potential-based short channel MOSFET model for circuit simulationKAN JIA; WEIFENG SUN; LONGXING SHI et al.Microelectronics journal. 2011, Vol 42, Num 10, pp 1169-1175, issn 0959-8324, 7 p.Article

Power-area evaluation of various double-gate RF mixer topologiesRAMMOHAN REDDY, M. V; SHARMA, D. K; PATIL, M. B et al.IEEE electron device letters. 2005, Vol 26, Num 9, pp 664-666, issn 0741-3106, 3 p.Article

Effect of Device Layout on the Stability of RF MOSFETsYONGHO OH; RIEH, Jae-Sung.IEEE transactions on microwave theory and techniques. 2013, Vol 61, Num 5, pp 1861-1869, issn 0018-9480, 9 p., 1Article

A compact model of MOSFET mismatch for circuit designGALUP-MONTORO, Carlos; SCHNEIDER, Marcio C; KLIMACH, Hamilton et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 8, pp 1649-1657, issn 0018-9200, 9 p.Article

Extraction of bias-dependent parasitic source/drain resistance in MOSFETs with an advanced mobility modelCHANG, Yang-Hua; YANG, Kun-Ying.Microelectronics and reliability. 2010, Vol 50, Num 2, pp 174-178, issn 0026-2714, 5 p.Article

A new constant-current technique for MOSFET parameter extractionLU, Chao-Yang; COOPER, James A.Solid-state electronics. 2005, Vol 49, Num 3, pp 351-356, issn 0038-1101, 6 p.Article

A novel scaling-parameter-dependent subthreshold swing model for double-gate (DG) SOI MOSFETs: including effective conducting path effect (ECPE)CHIANG, T. K.Semiconductor science and technology. 2004, Vol 19, Num 12, pp 1386-1390, issn 0268-1242, 5 p.Article

Recesseed source-drain (S/D) SOI MOSFETs with low S/D extension (SDE) external resistanceAHN, C. G; CHO, W. J; IM, K. J et al.IEEE international SOI conference. 2004, pp 207-208, isbn 0-7803-8497-0, 1Vol, 2 p.Conference Paper

Schottky-barrier-height engineering for strained-Si MOSFETsIKEDA, Keiji; YAMASHITA, Yoshimi; ENDOH, Akira et al.DRC : Device research conference. 2004, pp 111-112, isbn 0-7803-8284-6, 1Vol, 2 p.Conference Paper

  • Page / 191