MINIMIZATION OF LOGIC NETWORKS UNDER A GENERALIZED COST FUNCTION.MUROGA S; HUNGCHI LAI.1976; I.E.E.E. TRANS. COMPUTERS; U.S.A.; DA. 1976; VOL. 25; NO 9; PP. 893-907; BIBL. 21 REF.Article

USELESS PRIME IMPLICANTS OF INCOMPLETELY SPECIFIED MULTIPLE-OUTPUT SWITCHING FUNCTIONSCUTLER RB; MUROGA S.1980; INT. J. COMPUT. INF. SCI.; ISSN 0091-7036; USA; DA. 1980; VOL. 9; NO 4; PP. 337-350; BIBL. 4 REF.Article

LOGIC NETWORKS OF CARRY-SAVE ADDERSHUNG CHI LAI; MUROGA S.1982; IEEE TRANS. COMPUT.; ISSN 0018-9340; USA; DA. 1982; VOL. 31; NO 9; PP. 870-882; BIBL. 10 REF.Article

Parallel multipliers with NOR gates based on G-minimum addersGING-SHUNG YU; MUROGA, S.International journal of computer & information sciences. 1984, Vol 13, Num 2, pp 111-121, issn 0091-7036Article

Absolute minimization of completely specified switching functionsSUNG JE HONG; MUROGA, S.IEEE transactions on computers. 1991, Vol 40, Num 1, pp 53-65, issn 0018-9340, 13 p.Article

Automated design of MOS circuits and layoutBRYANT, P. K; MUROGA, S.Computer-aided design. 1986, Vol 18, Num 9, pp 489-496, issn 0010-4485Article

Parallel binary adders with a minimum number of connectionsSAKURAI, A; MUROGA, S.IEEE transactions on computers. 1983, Vol 32, Num 10, pp 969-976, issn 0018-9340Article

Derivation of minimal sums for completely specified functionsCUTLER, R. B; MUROGA, S.IEEE transactions on computers. 1987, Vol 36, Num 3, pp 277-292, issn 0018-9340Article

Design of MOS networks in single-rail input logic for incompletely specified functionsHUNG CHI LAI; MUROGA, S.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 3, pp 339-345, issn 0278-0070Article

Logic networks with a minimum number of NOR(NAND) gates for parity functions of n variablesHUNG CHI LAI; MUROGA, S.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 157-166, issn 0018-9340Article

Symmetric minimal covering problem and minimal PLA's with symmetric variablesMING HUEI YOUNG; MUROGA, S.IEEE transactions on computers. 1985, Vol 34, Num 6, pp 523-541, issn 0018-9340Article

Design of logic circuits with wired-logic utilizing transduction methodYAMASHITA, S; KAMBAYASHI, Y; MUROGA, S et al.Systems and computers in Japan. 1996, Vol 27, Num 11, pp 19-28, issn 0882-1666Article

Optimization methods for look-up table-type FPGAs based on permissible functionsYAMASHITA, S; KAMBAYASHI, Y; MUROGA, S et al.Systems and computers in Japan. 1996, Vol 27, Num 12, pp 92-101, issn 0882-1666Article

Analysis of Magnetic Flux Through Magnetic Film With Negative PermeabilityMUROGA, S; ASAZUMA, Y; ENDO, Y et al.IEEE transactions on magnetics. 2012, Vol 48, Num 11, pp 4320-4323, issn 0018-9464, 4 p.Conference Paper

High permeability and electromagnetic noise suppression characteristics of Fe―B―P sub-micron particle chains and their composites with NiZn―ferrite nanoparticlesYAO, Ch; SHIMADA, Y; MUROGA, S et al.Journal of alloys and compounds. 2013, Vol 554, pp 414-418, issn 0925-8388, 5 p.Article