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A 32K ASIC synchronous RAM using a two-transistor basic cellYUEN, A; TSAO, P; YIN, P et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 57-61, issn 0018-9200, 5 p.Article

A 14-ns 1-Mbit CMOS SRAM with variable bit organizationKOHNO, Y; WADA, T; ANAMI, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1060-1066, issn 0018-9200Article

A 25-ns low-power full-CMOS 1-Mbit (128K×8) SRAMCHU, S. T; DIKKEN, J; HARTGRING, C. D et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1078-1084, issn 0018-9200Article

Charle losses of N-doped trench cellsRISCH, L; MALY, R; BERGNER, W et al.Japanese journal of applied physics. 1988, Vol 27, Num 11, pp L2223-L2226, issn 0021-4922, part 2Article

Contribution à l'étude du test aléatoire de mémoires RAM = Study of the random test of RAM memoryFUENTES, Antoine; DAVID, René.1986, 110 pThesis

Optoelectronic dynamic random access memory cell utilizing a three-terminal N-channel self-aligned double-heterostructure optoelectronic switchTAYLOR, G. W; CRAWFORD, D. L; SIMMONS, J. G et al.Applied physics letters. 1989, Vol 54, Num 6, pp 543-545, issn 0003-6951, 3 p.Article

A 12-ns ECL I/O 256K×1-bit SRAM using a 1-υm BiCMOS technologyKERTIS, R. A; SMITH, D. D; BOWMAN, T. L et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1048-1053, issn 0018-9200Article

Dual-operating-voltage scheme for a single 5-V 16-Mbit DRAMHORIGUCHI, M; AOKI, M; TANAKA, H et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1128-1132, issn 0018-9200Article

Soft error rates in 64 K and 256 K DRAMsHAQUE, A. K. M. M; YATES, J; STEVENS, D et al.Electronics Letters. 1986, Vol 22, Num 22, pp 1188-1189, issn 0013-5194Article

FeRAM technology: Today and futureKUNISHIMA, Iwao; NAGEL, Nicolas.Proceedings - Electrochemical Society. 2003, pp 149-151, issn 0161-6374, isbn 1-56677-376-8, 3 p.Conference Paper

A 7.5-ns 32K×8 CMOS SRAMOKUYAMA, H; NAKANO, T; NISHIDA, S et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1054-1059, issn 0018-9200Article

An 18-ns 1-Mbit CMOS SRAMSHIMADA, H; TANGE, Y; TANIMOTO, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1073-1077, issn 0018-9200Article

Beam-induced seeded lateral epitaxy with suppressed impurity diffusion for a three-dimensional DRAM cell fabricationOHKURA, M; KUSUKAWA, K; SUNAMI, H et al.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 2, pp 333-339, issn 0018-9383, 7 p.Article

A 4-ns 4K×1-bit two-port BiCMOS SRAMTSEN-SHAU YANG; HOROWITZ, M. A; WOOLEY, B. A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1030-1040, issn 0018-9200Article

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devicesWONG, D. T; ADAMS, R. D; ARUP BHATTACHARYYA et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1095-1103, issn 0018-9200Article

Smart dual-port RAM: HD63310HAYASHI, S; ABE, M.Hitachi review. 1986, Vol 35, Num 5, pp 247-250, issn 0018-277XArticle

Using embedded objects for yield monitoringBAZAN, Greg; GRAVEL, Francis; HUISMAN, Leendert et al.IEEE / SEMI advanced semiconductor manufacturing conference. 2004, pp 124-128, isbn 0-7803-8312-5, 1Vol, 5 p.Conference Paper

A subnanosecond 5-kbit bipolar ECL RAMCHING-TE CHUANG; TANG, D. D; LI, G. P et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1265-1267, issn 0018-9200Article

Built- in testing of memory using an on-chip compact testing schemeKINOSHITA, K; SALUJA, K. K.IEEE transactions on computers. 1986, Vol 35, Num 10, pp 862-870, issn 0018-9340Article

Twisted bit-line architectures for multi-megabit DRAM'sHIDAKA, H; FUJISHIMA, K; MATSUDA, Y et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 21-27, issn 0018-9200, 7 p.Article

A three-dimensional static RAMINOUE, Y; SUGAHARA, K; KUSUNOKI, S et al.IEEE electron device letters. 1986, Vol 7, Num 5, pp 327-329, issn 0741-3106Article

The HM53462: 64 kbit×4 dual-port video RAM with logic functionsSATO, K; ISHIHARA, M; TANIMURA, N et al.Hitachi review. 1986, Vol 35, Num 5, pp 259-262, issn 0018-277XArticle

Novel integration technologies for highly manufacturable 32Mb FRAMKIM, H. H; SONG, Y. J; LEE, S. W et al.Symposium on VLSI technology. 2002, pp 210-211, isbn 0-7803-7312-X, 2 p.Conference Paper

Interactive and non-destructive verification of sram-descrambling with laserSTUFFER, A.Microelectronics and reliability. 2004, Vol 44, Num 9-11, pp 1669-1674, issn 0026-2714, 6 p.Conference Paper