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A 25-ns low-power full-CMOS 1-Mbit (128K×8) SRAMCHU, S. T; DIKKEN, J; HARTGRING, C. D et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1078-1084, issn 0018-9200Article

A 12-ns ECL I/O 256K×1-bit SRAM using a 1-υm BiCMOS technologyKERTIS, R. A; SMITH, D. D; BOWMAN, T. L et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1048-1053, issn 0018-9200Article

A 4-ns 4K×1-bit two-port BiCMOS SRAMTSEN-SHAU YANG; HOROWITZ, M. A; WOOLEY, B. A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1030-1040, issn 0018-9200Article

An 11-ns 8K×18 CMOS static RAM with 0.5-μm devicesWONG, D. T; ADAMS, R. D; ARUP BHATTACHARYYA et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1095-1103, issn 0018-9200Article

A 7.5-ns 32K×8 CMOS SRAMOKUYAMA, H; NAKANO, T; NISHIDA, S et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1054-1059, issn 0018-9200Article

An 18-ns 1-Mbit CMOS SRAMSHIMADA, H; TANGE, Y; TANIMOTO, K et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1073-1077, issn 0018-9200Article

New low current memory modes with giant magneto-resistance materialsRANMUTHU, K. T. M; POHM, A. V; DAUGHTON, J. M et al.IEEE transactions on magnetics. 1993, Vol 29, Num 6, pp 2593-2595, issn 0018-9464, 1Conference Paper

A three-dimensional static RAMINOUE, Y; SUGAHARA, K; KUSUNOKI, S et al.IEEE electron device letters. 1986, Vol 7, Num 5, pp 327-329, issn 0741-3106Article

A proposed new structure for SEU immunity in SRAM employing drain resistanceOCHOA, A. JR; AXNESS, C. L; WEAVER, H. T et al.IEEE electron device letters. 1987, Vol 8, Num 11, pp 537-539, issn 0741-3106Article

A 21-ns 32K×8 CMOS static RAM with a selectively pumped p-well arrayWANG, K. L; BADER, M. D; SOORHOLTZ, V. W et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 5, pp 704-711, issn 0018-9200Article

State space models using simplified routh approximation methodGOPALA RAO, K. A.Electronics Letters. 1992, Vol 28, Num 1, issn 0013-5194, p. 60Article

An 8-ns 256K ECL SRAM with CMOS memory array and battery backup capabilityVAN TRAN, H; SCOTT, D. B; PAK KUEN FUNG et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1041-1047, issn 0018-9200Article

A high-speed 1-kbit high electron mobility transistor static RAMSHENG, N. H; WANG, H. T; LEE, C. P et al.I.E.E.E. transactions on electron devices. 1987, Vol 34, Num 8, pp 1670-1675, issn 0018-9383, 1Article

Static memory element based on electron Y-branch switchHARTMANN, D; REITZENSTEIN, S; WORSCHECH, L et al.Electronics Letters. 2005, Vol 41, Num 6, pp 303-304, issn 0013-5194, 2 p.Article

A study of static RAM cell using the Lambda Bipolar Transistor (LBT)SARKAR, M; SATYAM, M; PRABHAKAR, A et al.Microelectronics journal. 1997, Vol 28, Num 1, pp 65-72, issn 0959-8324Article

Ontologies for knowledge representation in a computer-based patient recordBAYEGAN, Elisabeth; NYTRØ, Øystein; GRIMSMO, Anders et al.Proceedings - International Conference on Tools with Artificial Intelligence, TAI. 2002, pp 114-121, issn 1082-3409, isbn 0-7695-1849-4, 8 p.Conference Paper

A reprogrammable gate array and applications : Field programmable gate arraysTRIMBERGER, S.Proceedings of the IEEE. 1993, Vol 81, Num 7, pp 1030-1041, issn 0018-9219Article

A high-speed 16-kb GaAs SRAM of less than 5 ns using triple-level metal interconnectionNODA, M; MATSUE, S; SAKAI, M et al.I.E.E.E. transactions on electron devices. 1992, Vol 39, Num 3, pp 494-499, issn 0018-9383Article

A fast 32K×8 CMOS static RAM with address transition detectionCHENG-WEI CHEN; JIEH-PING PENG; SHYU, M.-Y. S et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 4, pp 533-537, issn 0018-9200Article

IC yield estimation at early stages of the design cycleCHEN, T; KIM, V.-K; TEGETHOFF, M et al.Microelectronics journal. 1999, Vol 30, Num 8, pp 725-732, issn 0959-8324Article

Corrected multiple upsets and bit reversals for improved 1-s resolution measurementsBRUCKER, G. J; STASSINOPOULOS, E. G; STAUFFER, C. A et al.IEEE transactions on nuclear science. 1994, Vol 41, Num 6, pp 2698-2705, issn 0018-9499, 2Article

Modelling semiconductor memory faultsVAN DE GOOR, A. J.Journal on communications. 1993, Vol 44, Num JUL, pp 8-13, issn 0866-5583Article

Un modèle de perception visuelle pour la vision artificielle = A model of visual perception for the artificial visionBEZERRA, Silvio José; CHERRUAULT, Yves.1993, 130 p.Thesis

Singel-word multiple-bit upsets in static random access devicesKOGA, R; PINKERTON, S. D; LIE, T. J et al.IEEE transactions on nuclear science. 1993, Vol 40, Num 6, pp 1941-1946, issn 0018-9499Conference Paper