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A simple model for the nanoscale surrounding-gate MOSFETJIMENEZ, D; INIGUEZ, B; SAENZ, J. J et al.International conference on microelectronics. 2004, isbn 0-7803-8166-1, 2Vol, vol 1, 265-267Conference Paper

Advanced SOI MOSFETs : structures and device physicsFAYNOT, O; VANDOOREN, A; GIFFARD, B et al.Proceedings - Electrochemical Society. 2005, pp 1-10, issn 0161-6374, isbn 1-56677-461-6, 10 p.Conference Paper

Drive-current enhancement in FinFETs using gate-induced stressTAN, Kian-Ming; LIOW, Tsung-Yang; LEE, Rinus T. P et al.IEEE electron device letters. 2006, Vol 27, Num 9, pp 769-771, issn 0741-3106, 3 p.Article

Junctionless Multiple-Gate Transistors for Analog ApplicationsTREVISOLI DORIA, Rodrigo; PAVANELLO, Marcelo Antonio; COLINGE, Jean-Pierre et al.I.E.E.E. transactions on electron devices. 2011, Vol 58, Num 8, pp 2511-2519, issn 0018-9383, 9 p.Article

Nickel-Silicide : Carbon Contact Technology for N-Channel MOSFETs With Silicon-Carbon Source/DrainLEE, Rinus T. P; YANG, Li-Tao; DONG ZHI CHI et al.IEEE electron device letters. 2008, Vol 29, Num 1, pp 89-92, issn 0741-3106, 4 p.Article

Spacer Removal Technique for Boosting Strain in n-Channel FinFETs With Silicon-Carbon Source and Drain StressorsLIOW, Tsung-Yang; TAN, Kian-Ming; LEE, Rinus T. P et al.IEEE electron device letters. 2008, Vol 29, Num 1, pp 80-82, issn 0741-3106, 3 p.Article

N-channel FinFETs with 25-nm gate length and schottky-barrier source and drain featuring ytterbium silicideLEE, Rinus T. P; EU-JIN LIM, Andy; TAN, Kian-Ming et al.IEEE electron device letters. 2007, Vol 28, Num 2, pp 164-167, issn 0741-3106, 4 p.Article

Effects of device layout on the drain breakdown voltages in MuGFETsJIN YOUNG KIM; CHONG GUN YU; JONG TAE PARK et al.Microelectronics and reliability. 2011, Vol 51, Num 9-11, pp 1547-1550, issn 0026-2714, 4 p.Conference Paper

Charge-based model enhancement for undoped surrounding-gate MOSFETsZHANG, L; HE, J.Electronics letters. 2009, Vol 45, Num 11, pp 569-570, issn 0013-5194, 2 p.Article

Multigate silicon MOSFETs for 45 nm node and beyondPOIROUX, T; VINET, M; FAYNOT, O et al.Solid-state electronics. 2006, Vol 50, Num 1, pp 18-23, issn 0038-1101, 6 p.Conference Paper

N-channel (110)-sidewall strained FinFETs with silicon-carbon source and drain stressors and tensile capping layerLIOW, Tsung-Yang; TAN, Kian-Ming; LEE, Rinus T. P et al.IEEE electron device letters. 2007, Vol 28, Num 11, pp 1014-1017, issn 0741-3106, 4 p.Article

Crystallographic-orientation-dependent GIDL current in Tri-gate MOSFETs under hot carrier stressJAE HOON LEE; JONG TAE PARK.Microelectronics and reliability. 2014, Vol 54, Num 9-10, pp 2315-2318, issn 0026-2714, 4 p.Conference Paper

Electrical characteristics of 20-nm junctionless Si nanowire transistorsPARK, Chan-Hoon; KO, Myung-Dong; KIM, Ki-Hyun et al.Solid-state electronics. 2012, Vol 73, pp 7-10, issn 0038-1101, 4 p.Article

Measurement of Capacitances in Multigate Transistors by Coulomb Blockade SpectroscopyHOFHEINZ, Max; JEHL, Xavier; SANQUER, Marc et al.IEEE transactions on nanotechnology. 2008, Vol 7, Num 1, pp 74-78, issn 1536-125X, 5 p.Article

A unified carrier-based model for undoped symmetric double-gate and surrounding-gate MOSFETsJIN HE; LINING ZHANG; JIAN ZHANG et al.Semiconductor science and technology. 2007, Vol 22, Num 12, pp 1312-1316, issn 0268-1242, 5 p.Article

A new method for the extraction of flat-band voltage and doping concentration in Tri-gate Junctionless TransistorsJEON, D.-Y; PARK, S. J; MOUIS, M et al.Solid-state electronics. 2013, Vol 81, pp 113-118, issn 0038-1101, 6 p.Article

An analytic model for threshold voltage shift due to quantum confinement in surrounding gate MOSFETs with anisotropic effective massYU YUAN; BO YU; SONG, Jooyoung et al.Solid-state electronics. 2009, Vol 53, Num 2, pp 140-144, issn 0038-1101, 5 p.Article

A Unified Analytic Drain-Current Model for Multiple-Gate MOSFETsBO YU; SONG, Jooyoung; YU YUAN et al.I.E.E.E. transactions on electron devices. 2008, Vol 55, Num 8, pp 2157-2163, issn 0018-9383, 7 p.Article

Performance estimation of junctionless multigate transistorsLEE, Chi-Woo; FERAIN, Isabelle; AFZALIAN, Aryan et al.Solid-state electronics. 2010, Vol 54, Num 2, pp 97-103, issn 0038-1101, 7 p.Article

High threshold voltage matching performance on gate-all-around MOSFETCATHIGNOL, Augustin; CROS, Antoine; HARRISON, Samuel et al.Solid-state electronics. 2007, Vol 51, Num 11-12, pp 1450-1457, issn 0038-1101, 8 p.Conference Paper

Simulation of multiple-gate quantum stub transistorSANTOS, Edval J. P; GUERRA, Alexandre B.Microelectronic engineering. 2005, Vol 81, Num 2-4, pp 544-552, issn 0167-9317, 9 p.Article

Multiple gate devices : advantages and challengesPOIROUX, T; VINET, M; FAYNOT, O et al.Microelectronic engineering. 2005, Vol 80, pp 378-385, issn 0167-9317, 8 p.Conference Paper

A two-dimensional model for interface coupling in triple-gate transistorsAKARVARDAR, Kerem; MERCHA, Abdelkarim; CRISTOLOVEANU, Sorin et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 4, pp 767-775, issn 0018-9383, 9 p.Article

Depletion-all-around operation of the SOI four-gate transistorAKARVARDAR, Kerem; CRISTOLOVEANU, Sorin; GENTIL, Pierre et al.I.E.E.E. transactions on electron devices. 2007, Vol 54, Num 2, pp 323-331, issn 0018-9383, 9 p.Article

Junctionless Π-gate transistor with indium gallium arsenide channelGUO, H. X; ZHANG, X; ZHU, Z et al.Electronics letters. 2013, Vol 49, Num 6, pp 402-404, issn 0013-5194, 3 p.Article

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