Continuous-flow variable-length memoryless linear regression architectureGARRIDO, M; GRAJAL, J.Electronics letters. 2013, Vol 49, Num 24, pp 1567-1569, issn 0013-5194, 3 p.Article

All-optical synchronization of self-pulsating laser diodes with frequency multiplication and divisionEGAN, A; HARLEY-STEAD, M; REES, P et al.Journal of modern optics (Print). 1998, Vol 45, Num 6, pp 1239-1248, issn 0950-0340Conference Paper

On the mode of electron bunch compression in O-type devices with automatic phase stabilizationBELYAVSKII, E. D.Journal of communications technology & electronics. 1997, Vol 42, Num 8, pp 932-935, issn 1064-2269Article

An Optimum Design for Integrated Switched-Capacitor Dickson Charge Pump Multipliers With Area Power BalanceTANZAWA, Toru.IEEE transactions on power electronics. 2014, Vol 29, Num 2, pp 534-538, issn 0885-8993, 5 p.Article

Regularised reweighted BPDN for compressed video sensingHAIXIAO LIU; BIN SONG; FANG TIAN et al.Electronics letters. 2014, Vol 50, Num 2, pp 83-84, issn 0013-5194, 2 p.Article

New efficient bit-parallel polynomial basis multiplier for special pentanomialsPARK, Sun-Mi; CHANG, Ku-Young; DOWON HONG et al.Integration (Amsterdam). 2014, Vol 47, Num 1, pp 130-139, issn 0167-9260, 10 p.Article

Bit-serial and digit-serial GF(2^m) Montgomery multipliers using linear feedback shift registersMORALES-SANDOVAL, M; FEREGRINO-URIBE, C; KITSOS, P et al.IET computers & digital techniques (Print). 2011, Vol 5, Num 2, pp 86-94, issn 1751-8601, 9 p.Article

Concurrent Error Detection in Bit-Serial Normal Basis Multiplication Over GF(2^m) Using Multiple Parity Prediction SchemesLEE, Chiou-Yng; PRAMOD KUMAR MEHER; JAGDISH CHANDRA PATRA et al.IEEE transactions on very large scale integration (VLSI) systems. 2010, Vol 18, Num 8, pp 1234-1238, issn 1063-8210, 5 p.Article

A method for speed optimized partial product reduction and generation of fast parallel multipliers using an algorithmic approachOKLOBDZIJA, V. G; VILLEGER, D; LIU, S. S et al.IEEE transactions on computers. 1996, Vol 45, Num 3, pp 294-306, issn 0018-9340Article

Multipliers to Shift the Through-Fault Protection Curve for Various Connections of Distribution TransformersSORRENTINO, Elmer; ALVAREZ, Manuel.IEEE transactions on power delivery. 2011, Vol 26, Num 3, pp 2055-2057, issn 0885-8977, 3 p.Article

Improved Cost Reversible Multiplier DesignCUTITARU, Mihail; BELFORE, Lee A.Computer design. International conferenceWorldComp'2011. 2011, pp 35-38, isbn 1-60132-173-2, 4 p.Conference Paper

Operation of a high-harmonic gyrofrequency multiplierBALKCUM, A. J; MCDERMOTT, D. B; LUHMANN, N. C et al.International journal of infrared and millimeter waves. 1995, Vol 16, Num 6, pp 985-998, issn 0195-9271Article

Design of Dual-Mode Frequency Multiplier With Schottky DiodesJIAN GUO; JIE XU; CHENG QIAN et al.IEEE microwave and wireless components letters. 2014, Vol 24, Num 8, pp 554-556, issn 1531-1309, 3 p.Article

Design of Low Power Parallel MultiplierBADGHARE, Rahul M; SANJIV KUMAR MANGAL; DESHMUKH, Raghavendra B et al.Journal of low power electronics (Print). 2009, Vol 5, Num 1, pp 31-39, issn 1546-1998, 9 p.Article

Memristive XOR for resistive multiplierSHIN, S; KIM, K; KANG, S.-M et al.Electronics letters. 2012, Vol 48, Num 2, pp 78-80, issn 0013-5194, 3 p.Article

Minimum-clock-cycle Itoh-Tsujii algorithm hardware implementation for cryptography applications over GF(2^m) fieldsPARRILLA, L; LLORIS, A; CASTILLO, E et al.Electronics letters. 2012, Vol 48, Num 18, pp 1126-1128, issn 0013-5194, 3 p.Article

Fixed-point multiplication: A probabilistic bit-pattern viewAHMADI, A; ZWOLINSKI, M.Microelectronics and reliability. 2011, Vol 51, Num 4, pp 790-796, issn 0026-2714, 7 p.Article

Low complexity architecture of bit parallel multipliers for GF/2^mSHOU, G; MAO, Z; HU, Y et al.Electronics letters. 2010, Vol 46, Num 19, pp 1326-1327, issn 0013-5194, 2 p.Article

A reduced I₂―I₁ model with an alternating minimisation algorithm for support recovery of multiple measurement vectorsXINPENG DU; DAIQIANG CHEN; LIZHI CHENG et al.IET signal processing (Print). 2013, Vol 7, Num 2, pp 112-119, issn 1751-9675, 8 p.Article

Coordination of directional overcurrent relay using evolutionary algorithm and linear programmingSUEIRO, Jose A; DIAZ-DORADO, Eloy; MIGUEZ, Edelmiro et al.Electrical power & energy systems. 2012, Vol 42, Num 1, pp 299-305, issn 0142-0615, 7 p.Article

Fixed-Width Group CSD Multiplier DesignKIM, Yong-Eun; CHO, Kyung-Ju; CHUNG, Jin-Gyun et al.IEICE transactions on information and systems. 2010, Vol 93, Num 6, pp 1497-1503, issn 0916-8532, 7 p.Article

The Golden Ratio EncoderDAUBECHIES, Ingrid; GÜNTÜRK, C. Sinan; YANG WANG et al.IEEE transactions on information theory. 2010, Vol 56, Num 10, pp 5097-5110, issn 0018-9448, 14 p.Article

Using error tolerance of target application for efficient reliability improvement of digital circuitsDOS SANTOS, G. G; MARQUES, E. C; DE B. NAVINER, L. A et al.Microelectronics and reliability. 2010, Vol 50, Num 9-11, pp 1219-1222, issn 0026-2714, 4 p.Conference Paper

Coordination of directional overcurrent relays using a novel method to select their settingsEZZEDDINE, M; KACZMAREK, R; IFTIKHAR, M. U et al.IET generation, transmission & distribution (Print). 2011, Vol 5, Num 7, pp 743-750, issn 1751-8687, 8 p.Article

Digit-Level Semi-Systolic and Systolic Structures for the Shifted Polynomial Basis Multiplication Over Binary Extension FieldsHARIRI, Arash; REYHANI-MASOLEH, Arash.IEEE transactions on very large scale integration (VLSI) systems. 2011, Vol 19, Num 11, pp 2125-2129, issn 1063-8210, 5 p.Article