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Low-Power Programmable FPGA Routing CircuitryANDERSON, Jason H; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2009, Vol 17, Num 8, pp 1048-1060, issn 1063-8210, 13 p.Article

Power estimation for large sequential circuitsKOZHAYA, Joseph N; NAJM, Farid N.IEEE transactions on very large scale integration (VLSI) systems. 2001, Vol 9, Num 2, pp 400-407, issn 1063-8210Article

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Low power VLSI design and technologyYEAP, Gary K; NAJM, Farid N.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, 122 p.Serial Issue

Low-power programmable routing circuitry for FPGAsANDERSON, Jason H; NAJM, Farid N.IEEE/ACM International Conference on Computer-Aided Design. 2004, isbn 0-7803-8702-3, 2Vol, vol2, 602-609Conference Paper

Dynamic range estimation for nonlinear systemsBIN WU; JIANWEN ZHU; NAJM, Farid N et al.IEEE/ACM International Conference on Computer-Aided Design. 2004, isbn 0-7803-8702-3, 2Vol, vol2, 660-667Conference Paper

A novel low-power FPGA routing switchANDERSON, Jason H; NAJM, Farid N.Custom integrated circuits conference. 2004, pp 719-722, isbn 0-7803-8495-4, 1Vol, 4 p.Conference Paper

A case for asymmetric-cell cache memoriesMOSHOVOS, Andreas; FALSAFI, Babak; NAJM, Farid N et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 7, pp 877-881, issn 1063-8210, 5 p.Article

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Retiming sequential circuits for low powerMONTEIRO, J; DEVADAS, S; GHOSH, A et al.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 323-340Article

Floorplan design with low power considerationsCHAO, K.-Y; WONG, D. F.International journal of high speed electronics and systems. 1996, Vol 7, Num 2, pp 305-322Article