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MINIMUM NAND-NOR SYNTHESIS OF S-FACTORIZED SUM OF PRODUCTS AND PRODUCT OF SUMS.MASSET GJ; TOSSER AJ.1977; INTERNATION. J. ELECTRON.; G.B.; DA. 1977; VOL. 43; NO 3; PP. 209-251; BIBL. 4 REF.Article

NAND GATES AND INVERTER SYNCHRONIZE CONTROL SIGNAL.WHITE RL.1976; ELECTRONICS; U.S.A.; DA. 1976; VOL. 49; NO 15; PP. 110-111Article

OSZACOWANIE WSKAZNIKOW NIEZAWODNOSCI JEDNORODNYCH KOMBINACYJNYCH SIECI LOGICZNYCH = ESTIMATION DES INDICES DE FIABILITE DE CIRCUITS LOGIQUES COMBINATOIRES CONTENANT SEULEMENT DES PARTS NON-ET NON-OUBARELA K.1977; ARCH. ELEKTROTECH.; POL; DA. 1977 PUBL. 1978; VOL. 26; NO 102; PP. 769-781; ABS. RUS/ENG/GER; BIBL. 13 REF.Article

MINIMAL TANT NETWORKS OF FUNCTIONS WITH DONT CARE'S AND SOME COMPLEMENTED INPUT VARIABLESVINK HA.1978; I.E.E.E. TRANS. COMPUTERS; USA; DA. 1978; VOL. 27; NO 11; PP. 1073-1078; BIBL. 16 REF.Article

Revue des problèmes équivalents de réalisation des circuits à base de ET-NON ne dépendant pas de la vitesseTSIRLIN, B. S.Izvestiâ Akademii nauk SSSR. Tehničeskaâ kibernetika. 1966, Num 2, pp 159-171, issn 0002-3388Article

Procedure for building test sequences for NAND-NOR networks with permanent stuck-at faultsKHALID-NACIRI, A; LOTFI, Z; TOSSER, A. J et al.International journal of electronics. 1985, Vol 59, Num 6, pp 759-769, issn 0020-7217Article

IMPLEMENTATION OF A TRANSCRIBED EXCLUSIVE OR OPERATORLOFTI Z; DUBUS D; TOSSER AJ et al.1978; INTERNATION. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 2; PP. 129-145; BIBL. 7 REF.Article

Logic networks with a minimum number of NOR(NAND) gates for parity functions of n variablesHUNG CHI LAI; MUROGA, S.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 157-166, issn 0018-9340Article

HEURISTIC UNLOADING PROCEDURE FOR NAND AND NOR GATESDUBUS D; TOSSER A.1978; INTERNATION. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 2; PP. 147-159; BIBL. 5 REF.Article

LOGIC NETWORKS OF CARRY-SAVE ADDERSHUNG CHI LAI; MUROGA S.1982; IEEE TRANS. COMPUT.; ISSN 0018-9340; USA; DA. 1982; VOL. 31; NO 9; PP. 870-882; BIBL. 10 REF.Article

OPPORTUNITY OF FACTORING IN NAND-NOR NETWORKS WHEN A MULTIPLE INVERTER IS AVAILABLEMASSET GJ; RABEL MJ; TOSSER AJ et al.1978; INTERN. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 3; PP. 289-298; BIBL. 2 REF.Article

SYNTHESIS OF A HAZARDLESS NAND NETWORK.AGUSA K; KAMBAYASHI Y.1975; SYST. COMPUTERS CONTROLS; U.S.A.; DA. 1975; VOL. 6; NO 2; PP. 13-21; BIBL. 12 REF.Article

A heuristic approach to synthesize boolean functions using tant networkHASAN BABU, Hafiz Md; RAFIQUL ISLAM, Md; NAZMUL, Rumana et al.IEEE International Symposium on Circuits and Systems. 2004, pp 373-376, isbn 0-7803-8251-X, 4 p.Conference Paper

Split-gate NAND flash memory at 120nm technology node featuring fast programming and eraseHSU, Cheng-Yuan; HUNG, Chi-Wei; HSUE, C. C et al.Symposium on VLSI Technology. sd, pp 78-79, isbn 0-7803-8289-7, 1Vol, 2 p.Conference Paper

Synthesis of multilevel feed-forward NAND networksSHIMIZU, K; SHUGANG WEI.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1986, Vol E69, Num 7, pp 785-787, issn 0387-236XArticle

A simple single element controlled triangular/square waveform generatorKHAN, A. A.International journal of electronics. 1984, Vol 57, Num 1, pp 91-95, issn 0020-7217Article

INJECTED VOLTAGE LOW-POWER CMOS FOR 3-VALUED LOGICMOUFTAH HT; SMITH KC.1982; IEE PROC., G; ISSN 0143-7089; GBR; DA. 1982; VOL. 129; NO 6; PP. 270-271; BIBL. 8 REF.Article

A MONTE CARLO BEASED CIRCUIT-LEVEL METHODOLOGY FOR ALGORITHMIC DESIGN OF MOS ISI STATIC RANDOM LOGIC CIRCUITS.PURI Y.1977; I.E.E.E. J. SOLID. STATES CIRCUITS; U.S.A.; DA. 1977; VOL. 12; NO 5; PP. 560-565; BIBL. 9 REF.Article

ALGEBRAIC OPTIMISATION OF NAND-NOR SWITCHING CIRCUITS.TOSSER A; DUBUS D.1977; COMPUTER J.; G.B.; DA. 1977; VOL. 20; NO 1; PP. 73-77; BIBL. 12 REF.Article

ESTIMATION DU NOMBRE D'ENTREES DES MICROMODULES DANS LES CIRCUITS LOGIQUESNOVIKOV SV; SUPRUN VP.1977; ELEKTRON. INFORM.-VERARBEIT. KYBERN.; DTSCH.; DA. 1977; VOL. 13; NO 7-8; PP. 345-349; ABS. ALLEM. ANGL.; BIBL. 3 REF.Article

Variations in performance degradation of CMOS NAND gates due to ionizing radiationMENICONI, M; BARRY, D. M; BETTS, D. C et al.Microelectronics and reliability. 1997, Vol 37, Num 6, pp 875-878, issn 0026-2714Article

A 0.7fJ/bit/search, 2.2ns search time hybrid type TCAM architectureCHOI, Sungdae; SOHN, Kyomin; LEE, Min-Wuk et al.IEEE International Solid-State Circuits Conference. 2004, pp 498-499, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 4-Mb NAND EEPROM with tight programmed Vt distributionMOMODOMI, M; TANAKA, T; IWATA, Y et al.IEEE journal of solid-state circuits. 1991, Vol 26, Num 4, pp 492-496, issn 0018-9200Article

Empirical minimization of the number of integrated circuits synthesizing a functionKHALID-NACIRI, A; RABEL, M; TOSSER, A.-J et al.International journal of electronics. 1986, Vol 60, Num 2, pp 251-256, issn 0020-7217Article

Probabilistic characterization of controllability in general homogeneous circuitsMAJUMDAR, A; SASTRY, S.Computer-aided design. 1993, Vol 25, Num 2, pp 76-93, issn 0010-4485Article

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