Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber lineBYONGHYO SHIM; SHANBHAG, Naresh R.IEEE transactions on signal processing. 2003, Vol 51, Num 1, pp 282-292, issn 1053-587X, 11 p.Article

Low-power MIMO signal processingLEI WANG; SHANBHAG, Naresh R.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 3, pp 434-445, issn 1063-8210, 12 p.Article

Energy-efficient soft error-tolerant digital signal processingSHIM, Byonghyo; SHANBHAG, Naresh R.IEEE transactions on very large scale integration (VLSI) systems. 2006, Vol 14, Num 4, pp 336-348, issn 1063-8210, 13 p.Article

Energy-efficiency bounds for deep submicron VLSI systems in the presence of noiseLEI WANG; SHANBHAG, Naresh R.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 2, pp 254-269, issn 1063-8210, 16 p.Article

Low-power filtering via adaptive error-cancellationLEI WANG; SHANBHAG, Naresh R.IEEE transactions on signal processing. 2003, Vol 51, Num 2, pp 575-583, issn 1053-587X, 9 p.Article

Local Calibration of Mechanistic-Empirical Pavement Design Guide for Flexible Pavement DesignMUTHADI, Naresh R; KIM, Y. Richard.Transportation research record. 2008, Num 2087, pp 131-141, issn 0361-1981, 11 p.Article

Joint Equalization and Coding for On-Chip Bus CommunicationSRIDHARA, Srinivasa R; BALAMURUGAN, Ganesh; SHANBHAG, Naresh R et al.IEEE transactions on very large scale integration (VLSI) systems. 2008, Vol 16, Num 3, pp 314-318, issn 1063-8210, 5 p.Article

A 640-Mb/s 2048-bit programmable LDPC decoder chipMANSOUR, Mohammad M; SHANBHAG, Naresh R.IEEE journal of solid-state circuits. 2006, Vol 41, Num 3, pp 684-698, issn 0018-9200, 15 p.Article

High-throughput LDPC decodersMANSOUR, Mohammad M; SHANBHAG, Naresh R.IEEE transactions on very large scale integration (VLSI) systems. 2003, Vol 11, Num 6, pp 976-996, issn 1063-8210, 21 p.Article

Robust and Energy Efficient Multimedia Systems via Likelihood Processing : NEW SOFTWARE/HARDWARE PARADIGMS FOR ERROR-TOLERANT MULTIMEDIA SYSTEMSABDALLAH, Rami A; SHANBHAG, Naresh R.IEEE transactions on multimedia. 2013, Vol 15, Num 2, pp 257-267, issn 1520-9210, 11 p.Article

Error-Resilient Low-Power Viterbi Decoder ArchitecturesABDALLAH, Rami A; SHANBHAG, Naresh R.IEEE transactions on signal processing. 2009, Vol 57, Num 12, pp 4906-4917, issn 1053-587X, 12 p.Article

Reliable low-power digital signal processing via reduced precision redundancySHIM, Byonghyo; SRIDHARA, Srinivasa R; SHANBHAG, Naresh R et al.IEEE transactions on very large scale integration (VLSI) systems. 2004, Vol 12, Num 5, pp 497-510, issn 1063-8210, 14 p.Article

A communication-theoretic design paradigm for reliable SOCsSHANBHAG, Naresh R.Design automation conference. 2004, isbn 1-58113-828-8, p. 76Conference Paper

DETERMINATION OF TIN COATING WEIGHT IN DIFFERENTIAL TINPLATE BY CLARKES TEST. = DETERMINATION, PAR LE TEST DE CLARKE, DU POIDS DE LA COUCHE D'ETAIN DES DIFFERENTS EMBALLAGES EN FER BLANCGOWRAMMA RV; MAHADEVIAH M; NARESH R et al.1982; JOURNAL OF FOOD SCIENCE AND TECHNOLOGY.; ISSN 0022-1155; IND; DA. 1982; VOL. 19; NO 2; PP. 83-84; BIBL. 3 REF.; 1 TABL.Article

Reduced complexity interpolation for soft-decoding of reed-solomon codesAHMED, Arshad; KOETTER, Ralf; SHANBHAG, Naresh R et al.IEEE International Symposium on Information Theory. 2004, isbn 0-7803-8280-3, 1Vol, p. 385Conference Paper

Efficient real coded genetic algorithm to solve the non-convex hydrothermal scheduling problemKUMAR, Sushil; NARESH, R.Electrical power & energy systems. 2007, Vol 29, Num 10, pp 738-747, issn 0142-0615, 10 p.Article

VLSI architectures for soft-decision decoding of reed-solomon codesAHMED, Arshad; KOETTER, Ralf; SHANBHAG, Naresh R et al.IEEE International Conference on Communications. 2004, isbn 0-7803-8533-0, vol5, 2584-2590Conference Paper

BER-Optimal Analog-to-Digital Converters for Communication LinksNARASIMHA, Rajan; MINWEI LU; SHANBHAG, Naresh R et al.IEEE transactions on signal processing. 2012, Vol 60, Num 7, pp 3683-3691, issn 1053-587X, 9 p.Article

Area-efficient high-throughput MAP decoder architecturesLEE, Seok-Jun; SHANBHAG, Naresh R; SINGER, Andrew C et al.IEEE transactions on very large scale integration (VLSI) systems. 2005, Vol 13, Num 8, pp 921-933, issn 1063-8210, 13 p.Article

Linear turbo equalization analysis via BER transfer and EXIT chartsLEE, Seok-Jun; SINGER, Andrew C; SHANBHAG, Naresh R et al.IEEE transactions on signal processing. 2005, Vol 53, Num 8, pp 2883-2897, issn 1053-587X, 15 p., 1Article

Performance analysis of the adaptive parity check matrix based soft-decision decoding algorithmAHMED, Arshad; KOETTER, Ralf; SHANBHAG, Naresh R et al.Asilomar Conference on Signals, Systems & Computers. 2004, isbn 0-7803-8622-1, 2Vol, vol 2, 1995-1999Conference Paper

Coding for system-on-chip networks : A unified frameworkSRIDHARA, Srinivasa R; SHANBHAG, Naresh R.Design automation conference. 2004, pp 103-106, isbn 1-58113-828-8, 4 p.Conference Paper

Strains of the intestinal spirochaete Brachyspira pilosicoli attach to and aggregate erythrocytesNARESH, R; HAMPSON, D. J.Letters in applied microbiology. 2014, Vol 58, Num 1, pp 65-69, issn 0266-8254, 5 p.Article

A novel forward-backward predictor based low-power DSP systemSHIM, Byonghyo; MING ZHANG; SHANBHAG, Naresh R et al.IEEE workshop on signal processing systems design and implementation. 2004, pp 331-336, isbn 0-7803-8504-7, 1Vol, 6 p.Conference Paper

Area and energy-efficient crosstalk avoidance codes for on-chip busesSRIDHARA, Srinivasa R; AHMED, Arshad; SHANBHAG, Naresh R et al.IEEE International Conference on Computer Design. 2004, pp 12-17, isbn 0-7695-2231-9, 1Vol, 6 p.Conference Paper