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MINIMUM NAND-NOR SYNTHESIS OF S-FACTORIZED SUM OF PRODUCTS AND PRODUCT OF SUMS.MASSET GJ; TOSSER AJ.1977; INTERNATION. J. ELECTRON.; G.B.; DA. 1977; VOL. 43; NO 3; PP. 209-251; BIBL. 4 REF.Article

OSZACOWANIE WSKAZNIKOW NIEZAWODNOSCI JEDNORODNYCH KOMBINACYJNYCH SIECI LOGICZNYCH = ESTIMATION DES INDICES DE FIABILITE DE CIRCUITS LOGIQUES COMBINATOIRES CONTENANT SEULEMENT DES PARTS NON-ET NON-OUBARELA K.1977; ARCH. ELEKTROTECH.; POL; DA. 1977 PUBL. 1978; VOL. 26; NO 102; PP. 769-781; ABS. RUS/ENG/GER; BIBL. 13 REF.Article

DESIGN OF NAND/NOR LOGIC NETWORKS - A NEW APPROACH.OM VIKAS.1977; J. INSTIT. ELECTRON. TELECOMMUNIC. ENGRS; INDIA; DA. 1977; VOL. 23; NO 5; PP. 303-306; BIBL. 8 REF.Article

Parallel binary adders with a minimum number of connectionsSAKURAI, A; MUROGA, S.IEEE transactions on computers. 1983, Vol 32, Num 10, pp 969-976, issn 0018-9340Article

Parallel multipliers with NOR gates based on G-minimum addersGING-SHUNG YU; MUROGA, S.International journal of computer & information sciences. 1984, Vol 13, Num 2, pp 111-121, issn 0091-7036Article

DESIGN METHOD FOR NEAR-OPTIMAL NOR LOGIC CIRCUITS.PESSEN D.1977; FLUIDICS QUART.; U.S.A.; DA. 1977; VOL. 9; NO 2; PP. 1-22; BIBL. 12 REF.Article

MINIMIZATION OF NAND-NOR NETWORKS BY FACTORING.MASSET GJ; TOSSER AJ.1976; INTERNATION. J. ELECTRON.; G.B.; DA. 1976; VOL. 41; NO 6; PP. 525-555; BIBL. 5 REF.Article

SCHNELLER DIGITAL/ANALOG-UMSETZER AUS ECL-NOR-GATTERN = CONVERTISSEURS RAPIDE NUMERIQUE/ANALYTIQUE AU MOYEN DE FILTRES NOR EN TECHNOLOGIE ECLSCHOLLE E.1979; ELEKTRONIK; DEU; DA. 1979; VOL. 28; NO 26; PP. 58-59Article

LOGIC FUNCTIONS USING INTERACTING TWO-STATE M.O.S. DEVICES.DARWISH MM; BOARD K.1978; ELECTRON. LETTERS; GBR; DA. 1978; VOL. 14; NO 15; PP. 482-483; BIBL. 3 REF.Article

Josephson NOR decoder circuit for Josephson memory arraysNAKANISHI, T; FIJITA, S.Japanese journal of applied physics. 1984, Vol 23, Num 8, pp 1002-1006, issn 0021-4922, 1Article

Procedure for building test sequences for NAND-NOR networks with permanent stuck-at faultsKHALID-NACIRI, A; LOTFI, Z; TOSSER, A. J et al.International journal of electronics. 1985, Vol 59, Num 6, pp 759-769, issn 0020-7217Article

High degree of satellite association and decreased nucleolar organizer activity in cystic fibrosis subjectsRAVIA, Y; LIEBERMAN, I; RAVE, A et al.American journal of medical genetics. 1987, Vol 28, Num 3, pp 593-605, issn 0148-7299Article

HEURISTIC UNLOADING PROCEDURE FOR NAND AND NOR GATESDUBUS D; TOSSER A.1978; INTERNATION. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 2; PP. 147-159; BIBL. 5 REF.Article

IMPLEMENTATION OF A TRANSCRIBED EXCLUSIVE OR OPERATORLOFTI Z; DUBUS D; TOSSER AJ et al.1978; INTERNATION. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 2; PP. 129-145; BIBL. 7 REF.Article

LOGIC NETWORKS OF CARRY-SAVE ADDERSHUNG CHI LAI; MUROGA S.1982; IEEE TRANS. COMPUT.; ISSN 0018-9340; USA; DA. 1982; VOL. 31; NO 9; PP. 870-882; BIBL. 10 REF.Article

OPPORTUNITY OF FACTORING IN NAND-NOR NETWORKS WHEN A MULTIPLE INVERTER IS AVAILABLEMASSET GJ; RABEL MJ; TOSSER AJ et al.1978; INTERN. J. ELECTRON.; GBR; DA. 1978; VOL. 45; NO 3; PP. 289-298; BIBL. 2 REF.Article

PERFORMANCES ET LIMITATIONS DES TECHNOLOGIES MONOCANAL N HMOS ACTUELLES: APPLICATION AUX CIRCUITS VLSI = PERFORMANCE FIGURES AND LIMITATIONS OF PRESENT N HMOS SINGLE CHANNEL TECHNOLOGIES: APPLICATION TO VLSI CIRCUITSAL ABDUL KADIR HUSSEIN ALI.1982; ; FRA; DA. 1982; 289 F.; 30 CM; BIBL. 52 REF.; TH. DOCT.-ING./GRENOBLE, I.N.P./1982Thesis

INJECTED VOLTAGE LOW-POWER CMOS FOR 3-VALUED LOGICMOUFTAH HT; SMITH KC.1982; IEE PROC., G; ISSN 0143-7089; GBR; DA. 1982; VOL. 129; NO 6; PP. 270-271; BIBL. 8 REF.Article

PROPAGATION DELAY TIME AND DELAY-POWER PRODUCT OF A SMALL-SIZED DSA-ED GATE CIRCUITHAYASHI Y.1978; I.E.E.E. J. SOLID-STATE CIRCUITS; USA; DA. 1978; VOL. 13; NO 5; PP. 726-728; BIBL. 4 REF.Article

A MONTE CARLO BEASED CIRCUIT-LEVEL METHODOLOGY FOR ALGORITHMIC DESIGN OF MOS ISI STATIC RANDOM LOGIC CIRCUITS.PURI Y.1977; I.E.E.E. J. SOLID. STATES CIRCUITS; U.S.A.; DA. 1977; VOL. 12; NO 5; PP. 560-565; BIBL. 9 REF.Article

ALGEBRAIC OPTIMISATION OF NAND-NOR SWITCHING CIRCUITS.TOSSER A; DUBUS D.1977; COMPUTER J.; G.B.; DA. 1977; VOL. 20; NO 1; PP. 73-77; BIBL. 12 REF.Article

Logic networks with a minimum number of NOR(NAND) gates for parity functions of n variablesHUNG CHI LAI; MUROGA, S.IEEE transactions on computers. 1987, Vol 36, Num 2, pp 157-166, issn 0018-9340Article

A design for an efficient NOR-gate only, binary-ripple adder with carry-completion-detection logicSALOMON, D.Computer journal (Print). 1987, Vol 30, Num 3, pp 283-285, issn 0010-4620Article

A 1K-gate GaAs gate arrayIKAWA, Y; TOYODA, N; MOCHIZUKI, M et al.IEEE journal of solid-state circuits. 1984, Vol 19, Num 5, pp 721-728, issn 0018-9200Article

A symmetric CMOS NOR gate for high-speed applicationsJOHNSON, M. G.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1233-1236, issn 0018-9200Article

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