kw.\*:("Plan masse")
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TCG-S: Orthogonal coupling of P*-admissible representations for general floorplansLIN, Jai-Ming; CHANG, Yao-Wen.Design automation conference. 2002, pp 842-847, isbn 1-58113-461-4, 6 p.Conference Paper
A new placement method for direct mapping into LUT-based FPGAsABKE, Joerg; BARKE, Erich.Lecture notes in computer science. 2001, pp 27-36, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Evaluateur topologique prédictif pour la génération automatique des plans de masse de circuits VLSI = Predictive topological evaluator for the automatic generation of VLSI circuit ground surfacesDA LUZ REIS, Ricardo Augusto.1983, 353 pThesis
High voltage microwave DC block for microstrip ground planesKOSCICA, T. E.Electronics Letters. 1990, Vol 26, Num 16, pp 1287-1288, issn 0013-5194Article
New clustering approach to chip floorplan using functional dataHARADA, I; ADACHI, T.Electronics Letters. 1987, Vol 23, Num 17, pp 900-902, issn 0013-5194Article
Enumerating floorplans with n roomsNAKANO, Shin-Ichi.Lecture notes in computer science. 2001, pp 107-115, issn 0302-9743, isbn 3-540-42985-9Conference Paper
EVALUATEUR TOPOLOGIQUE POUR CIRCUITS VLSI: MODULE D'EVALUATION DE ROM = TOPOLOGICAL EVALUATOR FOR VLSI CIRCUITS: ROM EVALUATION MODULEREIS RICARDO.1981; ; FRA; DA. 1981; IMAG-RR/252; 51 P.; 30 CM; ABS. ENG; BIBL. 1 P.;[RAPP. RECH.-LAB. INFORM. MATH. APPL. GRENOBLE; VOL. RR-252]Report
Óbidos : Un complexe touristique haut en architecture = Óbidos: A tourist complex rich in architectureALBERT, Marie-Douce.Le Moniteur des travaux publics et du bâtiment. 2012, Num NOV, pp 30-31, issn 0026-9700, 2 p., NSArticle
Construction plan of Tohoku through lineKOBAYASHI, Chika.Japanese railway engineering. 2009, Vol 49, Num 1, issn 0448-8938, a, 11-13 [4 p.]Article
Usinf CAD in construction field engineeringABUDAYYEH, O; MALETIC, V.Advances in engineering software (1992). 1994, Vol 20, Num 1, pp 13-17, issn 0965-9978Article
Complex images of an electric dipole in homogeneous and layered dielectrics beween two ground planesYANG, J. J; CHOW, Y. L; HOWARD, G. E et al.IEEE transactions on microwave theory and techniques. 1992, Vol 40, Num 3, pp 595-600, issn 0018-9480Article
Depth-first-search and dynamic programming algorithms for efficient CMOS cell generationBAR-YEHUDA, R; FELDMAN, J. A; PINTER, R. Y et al.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 7, pp 737-743, issn 0278-0070Article
Mismatch simulation for layout sensitive parameters of IC components and devicesTRÖSTER, G; TOMASZEWSKI, P.IEEE transactions on computer-aided design of integrated circuits and systems. 1989, Vol 8, Num 2, pp 101-107, issn 0278-0070Article
Algorithms for physical design of sea-of-gates chipsSHRAGOWITZ, E; LEE, J; SAHNI, S et al.Computer-aided design. 1988, Vol 20, Num 7, pp 382-397, issn 0010-4485Article
Canonical decomposition, realizer, Schnyder labeling and orderly spanning trees of plane graphs: (Extended abstract)MIURA, Kazuyuki; AZUMA, Machiko; NISHIZEKI, Takao et al.Lecture notes in computer science. 2004, pp 309-318, issn 0302-9743, isbn 3-540-22856-X, 10 p.Conference Paper
An automated method for overlay sample plan optimization based on spatial variation modelingXUEMEI CHEN; PREIL, Moshe E; LE GOFF-DUSSABLE, Mathilde et al.SPIE proceedings series. 2001, pp 257-266, isbn 0-8194-4030-2Conference Paper
ITER generic site layout and servicesAHLFELD, C; CHUYANOV, V; DILLING, D et al.SOFT : Symposium on fusion technology. 1998, 2Vol, Vol 2, 1689-1692Conference Paper
APPROCHE MULTICRITERE POUR L'AIDE AU CHOIX D'UNE SOLUTION DE PLAN MASSE BATIMENT = MULTICRITERIA APPROACH ALLOWING TO CHOOSE A SOLUTION OF BUILDING LAYOUT PLANZatar, Abdallah; Boissier, Daniel.1997, 182 p.Thesis
ALSO: a system for chip floorplan designHSU, Y. C; KUBITZ, W. J.Integration (Amsterdam). 1988, Vol 6, Num 2, pp 127-146, issn 0167-9260Article
Placing, routing, and editing virtual FPGAsLAGADEC, Loïc; LAVENIER, Dominique; FABIANI, Erwan et al.Lecture notes in computer science. 2001, pp 357-366, issn 0302-9743, isbn 3-540-42499-7Conference Paper
Höherer Störabstand für Embedded-Systeme = Always less perturbations for embedded systemsBAKER, B. C.Embedded engineering. 2000, Num 1, pp 29-32, issn 1616-3370Article
Knowledge-based approach to overall configuration of multistory office buildings = Méthode par base de connaissances pour la conception générale de bâtiments de bureau élevésBEDARD, C; RAVI, M.Journal of computing in civil engineering. 1991, Vol 5, Num 4, pp 336-353, issn 0887-3801Article
A logic-to-logic comparator for VLSI layout verificationMAURER, P. M; SCHAPIRA, A. D.IEEE transactions on computer-aided design of integrated circuits and systems. 1988, Vol 7, Num 8, pp 897-907, issn 0278-0070Article
Linear placement algorithms and applications to VLSI designCHUNG-KUAN CHENG.Networks (New York, NY). 1987, Vol 17, Num 4, pp 439-464, issn 0028-3045Article
Algorithm for incremental compaction of geometrical layoutsNANDY, S. K; PATNAIK, L. M.Computer-aided design. 1987, Vol 19, Num 5, pp 257-265, issn 0010-4485Article