Digital Signal ProcessingTALLA, Deepu.International journal of embedded systems (Print). 2009, Vol 4, Num 1, issn 1741-1068, 99 p.Serial Issue

Advanced signal processing algorithms, architectures, and implementations XIII (San Diego CA, 6-8 August 2003)Luk, Franklin T.SPIE proceedings series. 2003, isbn 0-8194-5078-2, X, 620 p, isbn 0-8194-5078-2Conference Proceedings

Implementation of Serpent encryption algorithm on 24-bit DSP processorIVANCIC, Dorian; RUNJE, Davor; KOVAC, Mario et al.International symposium on image and signal processing and analysis. 2001, pp 411-416, isbn 953-96769-4-0Conference Paper

Optimization of DSP virtual machine (DSPVM<^TM>) in embedded DSPSUN, Jiangbo; CHEN, Houjin.International Conference on Signal Processing. 2004, pp 136-139, isbn 0-7803-8406-7, 4 p.Conference Paper

A fast and accurate validation technique for operating system in multi-processor system-on-chip designBACIVAROV, Iuliana; JERRAYA, Ahmed A; YOO, Sungjoo et al.SPIE proceedings series. 2003, pp 342-348, isbn 0-8194-5100-2, 7 p.Conference Paper

SPOT: Development tool for software pipeline optimization for VLIW-DSPs used in real-time image processingFÜRTLER, Johannes; MAYER, Konrad J; KRATTENTHALER, Werner et al.Real-time imaging (Print). 2003, Vol 9, Num 6, pp 387-399, issn 1077-2014, 13 p.Article

The Investigator® : A studio-based DSP learning paradigmFRANKEL, Ryan; NEZIS, Nicholas; TAYLOR, Fred et al.ICASSP. 2004, isbn 0-7803-8484-9, vol V, 1013-1016Conference Paper

CSNDSP 2000CLARKE, Roger J.IEE proceedings. Circuits, devices and systems. 2002, Vol 149, Num 3, issn 1350-2409, 57 p.Conference Proceedings

Implementation of a multi-channel G.723.1 annex A using a DSPCHOI, Yong-Soo; AHN, Chang-Kyu; KANG, Tae-Ik et al.Interantional conference on consumer electronics. 2002, pp 320-321, isbn 0-7803-7300-6, 2 p.Conference Paper

DSP with FPGAs: A Xilinx/Simulink-based Course and LaboratoryMEYER-BAESE, Uwe; VERA, A; MEYER-BAESE, A et al.Proceedings of SPIE, the International Society for Optical Engineering. 2008, Vol 6979, pp 697907.1-697907.12, issn 0277-786X, isbn 978-0-8194-7170-3 0-8194-7170-4Conference Paper

Design methods for DSP systemsRUPP, Markus; WESS, Bernhard; BHATTACHARYYA, Shuvra S et al.EURASIP journal on applied signal processing. 2006, Vol 2006, Num 14, issn 1110-8657, 174 p.Serial Issue

Special issue on the EEEE 2004 ISSCC: Digital, technology directions, memory, and signal processingKONSTADINIDIS, Georgios K; CHANDRAKASAN, Anantha; NATARAJAN, Sreedhar et al.IEEE journal of solid-state circuits. 2005, Vol 40, Num 1, issn 0018-9200, 350 p.Conference Proceedings

Cell Broadband Engine architecture as a DSP platformSZUMSKI, Karol; MALANOWSKI, Mateusz.Proceedings of SPIE, the International Society for Optical Engineering. 2009, Vol 7502, issn 0277-786X, isbn 978-0-8194-7813-9 0-8194-7813-X, 1Vol, 75022O.1-75022O.6Conference Paper

Low power multi-segment sequential one hot addressing architectureTAN, K.-C. B; ARSLAN, T.IEE proceedings. Circuits, devices and systems. 2006, Vol 153, Num 2, pp 159-166, issn 1350-2409, 8 p.Article

A novel processor architecture for network applicationsRAMAZANI, A; DIOU, C; MONTEIRO, F et al.International conference on signals and electronic systems. 2005, pp 421-424, isbn 83-906074-7-6, 1Vol, 4 p.Conference Paper

Advanced signal processing algorithms, architectures, and implementations XIV (Denver CO, 4-6 August 2004)Luk, Franklin T.SPIE proceedings series. 2004, isbn 0-8194-5497-4, VIII, 464 p, isbn 0-8194-5497-4Conference Proceedings

ELMMA : A new low power high-speed adder for RNSPATEL, R. A; BENAISSA, M; POWELL, N et al.IEEE workshop on signal processing systems design and implementation. 2004, pp 95-100, isbn 0-7803-8504-7, 1Vol, 6 p.Conference Paper

A full-rate software implementation of an IEEE 802.11A compliant digital baseband transmitterMEEUWSEN, Michael J; SATTARI, Omar; BAAS, Bevan M et al.IEEE workshop on signal processing systems design and implementation. 2004, pp 124-129, isbn 0-7803-8504-7, 1Vol, 6 p.Conference Paper

A comparative study of the suitability of a custom computing machine and a vliw DSP for use in 3G applicationsNEEL, James; SRIKANTESWARA, Srikathyayani; REED, Jeffrey H et al.IEEE workshop on signal processing systems design and implementation. 2004, pp 188-193, isbn 0-7803-8504-7, 1Vol, 6 p.Conference Paper

A scaled DCT architecture with the CORDIC algorithmSUNGWOOK YU; SWARTZLANDER, Earl E; FELLOW et al.IEEE transactions on signal processing. 2002, Vol 50, Num 1, pp 160-167, issn 1053-587XArticle

Multi-DSP-Systeme: Kaskadierbare PCI-karten für professionelle Musikapplikationen = Multi-DSP system : cascade PCI cards for professional musical applicationsBARTSCHT, Frank.Embedded engineering. 2002, Num 4, pp 26-27, issn 1616-3370, 2 p.Article

600Mhz DSP for baseband processing in 3G base stationsWOLF, Tod; HOCEVAR, Dale; GATHERER, Alan et al.Custom integrated circuits conference. 2002, pp 393-396, isbn 0-7803-7250-6, 4 p.Conference Paper

Study and implementation of complementary Golay Sequences for PAR reduction in OFDM signalsGIL JIMENEZ, Victor P; SANCHEZ FERNANDEZ, Matilde; GARCIA ARMADA, Ana et al.IEEE Mediterranean electrotechnical conference. 2002, pp 198-203, isbn 0-7803-7527-0, 6 p.Conference Paper

Systems-on-chip: what are the limits? : System on chipROZA, E.Electronics & communication engineering journal. 2001, Vol 13, Num 6, pp 249-255, issn 0954-0695Article

A DSP+FPGA based real-time histogram equalization system of infrared imageGU DONGSHENG; YANG NANSHENG; PI DEFU et al.SPIE proceedings series. 2001, pp 160-165, isbn 0-8194-4341-7Conference Paper