Pascal and Francis Bibliographic Databases


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Results 1 to 25 of 14503

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Constant time algorithm for template matching on a reconfigurable array of processorsHORNG, S. J.Computer journal (Print). 1993, Vol 36, Num 3, pp 246-253, issn 0010-4620Article

A variable delay line PLL for CPU-coprocessor synchronizationJOHNSON, M. G; HUDSON, E. L.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1218-1223, issn 0018-9200Article

Innateness, universal grammar, and emergentismO'GRADY, William.Lingua (Haarlem. Print). 2008, Vol 118, Num 4, pp 620-631, issn 0024-3841, 12 p.Article

Server scheduling in the weighted <script small 1>p normBANSAL, Nikhil; PRUHS, Kirk.Lecture notes in computer science. 2004, pp 434-443, issn 0302-9743, isbn 3-540-21258-2, 10 p.Conference Paper

An efficient dictionary machine using hexagonal processor arraysYOUN, H. Y; LEE, J. Y.IEEE transactions on parallel and distributed systems. 1996, Vol 7, Num 3, pp 266-273, issn 1045-9219Article

A new graph approach to minimizing processor fragmentation in hypercube multiprocessorsQUING YANG; HONG WANG.IEEE transactions on parallel and distributed systems. 1993, Vol 4, Num 10, pp 1165-1171, issn 1045-9219Article

Optical implementations of associative networks with versatile adaptive learning capabilitiesFISHER, A. D; LIPPINCOTT, W. L; LEE, J. N et al.Applied optics. 1987, Vol 26, Num 23, pp 5039-5054, issn 0003-6935Article

A Skorokhod Problem formulation and large deviation analysis of a processor sharing modelDUPUIS, P; RAMANAN, K.Queueing systems. 1998, Vol 28, Num 1-3, pp 109-124, issn 0257-0130Article

From HUP to MCP: Analogies and extended performancesTODINI, Ezio.Journal of hydrology (Amsterdam). 2013, Vol 477, pp 33-42, issn 0022-1694, 10 p.Article

Adaptively mapping code in an intelligent memory architectureSOLIHIN, Yan; JAEJIN LEE; TORRELLAS, Josep et al.Lecture notes in computer science. 2001, pp 71-84, issn 0302-9743, isbn 3-540-42328-1Conference Paper

Fast encryption algorithm spectr-H64GOOTS, Nick D; MOLDOVYAN, Alexander A; MOLDOVYAN, Nick A et al.Lecture notes in computer science. 2001, pp 275-286, issn 0302-9743, isbn 3-540-42103-3Conference Paper

A digital signal processor for modem applicationDOI, K; SASAKI, Y; KUSANO, T et al.NEC research & development. 1989, Num 92, pp 33-38, issn 0547-051X, 6 p.Article

Der integrierte Signalprozessor = Le processeur intégré = The integrated signal processorLACROIX, A.Nachrichtentechnik. Elektronik. 1985, Num 6, pp 231-233, issn 0323-4657Article

Microprogrammable pipelined vector processorMADESWARAN, V; MATHIALAGAN, A.Computers in industry. 1990, Vol 13, Num 4, pp 367-370, issn 0166-3615Article

Design of a pipelined optoelectronic processorMCARDLE, N; NARUSE, M; OKUTO, A et al.SPIE proceedings series. 1998, pp 302-305, isbn 0-8194-2949-XConference Paper

Design considerations for an optimal symbolic processing architectureDERSTINE, M. W; GUHA, A.Optical engineering (Bellingham. Print). 1989, Vol 28, Num 4, pp 434-446, issn 0091-3286, 13 p.Article

Vers un processeur de signal aisément utilisable = Towards an easy-to-use D.S.POKSMAN, J; MARTINEZ GARCIA-MORENO, C. A.T.S. Traitement du signal. 1989, Vol 6, Num 4, pp 257-267, 11 p.Article

A new type fading simulator with DSPKAMIO, Y; SAMPEI, S; SASAOKA, H et al.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1987, Vol 70, Num 4, pp 379-382, issn 0387-236XArticle

Ein geschlossenes Konzept zur effizienten Behandlung der Deadlockproblematik in Betriebssystemen = Un concept élaboré pour le traitement efficace des problèmes d'interblocage apparaissant dans les systèmes d'exploitation = An elaborate concept for efficient handling of deadlock problems appearing in operating systemsZÖBEL, D.Elektronische Rechenanlagen. 1984, Vol 26, Num 1, pp 3-12, issn 0013-5720Article

On finite capacity processor-shared queuesKNESSL, C.SIAM journal on applied mathematics (Print). 1990, Vol 50, Num 1, pp 264-287, issn 0036-1399, 24 p.Article

Assembler für den Signalprozessor μPD 77230 = Assembler for signal processor μPD 77230RIEKEN, R; OLEY, R.Wissenschaftliche Zeitschrift der Technischen Universität Karl-Marx-Stadt. 1989, Vol 31, Num 4, pp 533-540, issn 0863-0615, 8 p.Article

Logical arithmeticCLEARY, J. G.Future computing systems. 1987, Vol 2, Num 2, pp 125-149Article

A triple-level wired 24K-gate CMOS gate arraySAIGO, T; NIWA, K; OHTO, T et al.IEEE journal of solid-state circuits. 1985, Vol 20, Num 5, pp 1005-1011, issn 0018-9200Article

Contrôleurs de télécommunicationsFRADIN,, 13 p.Article

Radix-2n multiplier structures: a structured design methodologyIBRAHIM, M. K.IEE proceedings. Part E. Computers and digital techniques. 1993, Vol 140, Num 4, pp 185-190, issn 0143-7062Article

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