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Results 1 to 25 of 1280

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A reconfigurable array for solving linear system of equations by LU-decomposition methodBEN CHEN; ONODA, M.Transactions of the Institute of Electronics and Communication Engineers of Japan. Section E. 1988, Vol 71, Num 9, pp 829-832, issn 0387-236XArticle

Systolic modular exponentiationTIOUNTCHIK, A. A.Lecture notes in computer science. 1997, pp 404-405, issn 0302-9743, isbn 3-540-63371-5Conference Paper

A hidden surface and shading processor (HSSP) with a systolic architectureNISHIZAWA, T; OHGI, T; KAMIYAMA, H et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1236-1240, issn 0018-9200Article

Improved systolic array for linear discriminant function classifierCHIN-LIANG WANG; CHE-HO WEI; SIN-HORNG CHEN et al.Electronics Letters. 1986, Vol 22, Num 2, pp 85-86, issn 0013-5194Article

Architecture of a CMOS correlatorCORRY, A; PATEL, K.GEC journal of research. 1983, Vol 1, Num 1, pp 35-38, issn 0264-9187Article

On optimal parallelization of sorting networksGANNETT, E; KOTHARI, S. C; HSU-CHUN YEN et al.Theoretical computer science. 1990, Vol 76, Num 2-3, pp 331-341, issn 0304-3975, 11 p.Article

Efficient one-dimensional systolic array realization of the discrete Fourier transformBERALDIN, J. A; ABOULNASR, T; STEENAART, W et al.IEEE transactions on circuits and systems. 1989, Vol 36, Num 1, pp 95-100, issn 0098-4094, 6 p.Article

A systolic array for the longest common subsequence problemROBERT, Y; TCHUENTE, M.Information processing letters. 1985, Vol 21, Num 4, pp 191-198, issn 0020-0190Article

Efficient bit-level systolic arrays for inner produit computationURQUHART, R. B; WOOD, D.GEC journal of research. 1984, Vol 2, Num 1, pp 52-55, issn 0264-9187Article

Optimised bit level systolic array for convolutionMCCANNY, J. V; MCWHIRTER, J. G; WOOD, K et al.IEE proceedings. Part F. Communications, radar and signal processing. 1984, Vol 131, Num 6, pp 632-637, issn 0143-7070Article

The application of a sequence notation to the design of systolic computationsRAMI MELHEM; GUERRA, C.BIT (Nordisk Tidskrift for Informationsbehandling). 1989, Vol 29, Num 3, pp 409-427, issn 0006-3835Article

Solution of dense linear systems on an optimal systolic architectureAHMED EL-AMAWY.Computers & electrical engineering. 1987, Vol 13, Num 3-4, pp 177-193, issn 0045-7906Article

Stability of recursive QRD-LS algorithms using finite-precision systolic array implementationLEUNG, H; HAYKIN, S.IEEE transactions on acoustics, speech, and signal processing. 1989, Vol 37, Num 5, pp 760-763, issn 0096-3518, 4 p.Article

Systolic array for all-nearest-neighbours problemPETKOV, N.Electronics Letters. 1987, Vol 23, Num 24, pp 1259-1260, issn 0013-5194Article

Smart quasiserial post processor for optical systolic systemsKARIM, M. A.Applied optics. 1991, Vol 30, Num 8, pp 910-912, issn 0003-6935Article

Block LU decomposition of a band matrix on a systolic array = Décomposition LU par blocs d'une matrice bande sur un réseau systoliqueROBERT, Yves.Rapport de recherche - IMAG. 1984, Num 452, issn 0750-7380, 1-[23] pReport

Systolic convolution arraySIMONS, J. A. E.Electronics Letters. 1983, Vol 19, Num 21, issn 0013-5194, 874Article

Using polynomic embedding for neural network designPORTER, W. A.IEEE Transactions on circuits and systems. II : Analog and digital signal processing. 1992, Vol 39, Num 6, pp 369-376Article

Systolic sorting in a sequential input/output environmentAKL, S. G; SCHMECK, H.Parallel computing. 1986, Vol 3, Num 1, pp 11-23, issn 0167-8191Article

A fast modular exponentiation for RSA on systolic arraysHAN, Y; MITCHELL, C. J; GOLLMANN, D et al.International journal of computer mathematics. 1997, Vol 63, Num 3-4, pp 215-226, issn 0020-7160Article

A faster linear systolic algorithm for recovering a longest common subsequenceLECROQ, T; LUCE, G; MYOUPO, J. F et al.Information processing letters. 1997, Vol 61, Num 3, pp 129-136, issn 0020-0190Article

Systolic architectures for the manipulator inertia matrixMASOUD AMIN-JAVAHERI; ORIN, D. E.IEEE transactions on systems, man, and cybernetics. 1988, Vol 18, Num 6, pp 939-951, issn 0018-9472Article

Fitted diagonals for reducing I/O bandwidth in systolic systemsSUROS, R; MONTAGNE, E.Information processing letters. 1987, Vol 25, Num 5, pp 335-341, issn 0020-0190Article

VLSI architectures for the computation of uniform B-spline curvesMEENAKSHI SUNDARAM GOPI; SWAMI MANOHAR.Microprocessing and microprogramming. 1994, Vol 40, Num 9, pp 617-626, issn 0165-6074Article

Simulation des algorithmes systoliques = Simulation of systolic algorithmsBENAINI, A.TSI. Technique et science informatiques. 1991, Vol 10, Num 1, pp 23-33, issn 0752-4072, 11 p.Article

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