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PERFORMANCE-RELATED ANALYSES FOR COMPUTING SYSTEMS WITH HIGH RELIABILITYKAJIYAMA M; OSAKI S.1979; SYST. COMPUT. CONTROLS; ISSN 0096-8765; USA; DA. 1979 PUBL. 1981; VOL. 10; NO 6; PP. 32-40; BIBL. 12 REF.Article

A SYSTEMATIC APPROACH TO DESIGN THE RECONFIGURATION SCHEME OF FAULT-TOLERANT SYSTEMSWEN LIANG CHEN; MING HWA JING.1981; COMPUT. ELECTR. ENG.; ISSN 0045-7906; USA; DA. 1981; VOL. 8; NO 3; PP. 223-228; BIBL. 4 REF.Article

PARALLEL PROCESSING WITH AN ARRAY OF MICROCOMPUTERSBRAUNLEDER B; KOBER R.1981; MICROPROCESS. MICROSYST.; ISSN 0141-9331; GBR; DA. 1981; VOL. 5; NO 6; PP. 241-245; BIBL. 10 REF.Article

Fault diagnosis and system reconfiguration of fault-tolerant system with majority votingYONEDA, T; KAWAMURA, T; FURUYA, K et al.Systems, computers, controls. 1985, Vol 16, Num 1, pp 9-17, issn 0096-8765Article

The MorphoSys parallel reconfigurable systemGUANGMING LU; SINGH, H; LEE, M.-H et al.Lecture notes in computer science. 1999, pp 727-734, issn 0302-9743, isbn 3-540-66443-2Conference Paper

Du microprocesseur au circuit FPGA : Une analyse sous l'angle de la reconfiguration = From microprocessor to the FPGA circuit: an analysis in the point of view of reconfigurationDAVID, Raphaël; LAVENIER, Dominique; PAILLEMENT, Sébastien et al.TSI. Technique et science informatiques. 2005, Vol 24, Num 4, pp 395-422, issn 0752-4072, 28 p.Article

A decomposition method to support the configuration / reconfiguration of production systemsCOLLEDANI, M; TOLIO, T.CIRP annals. 2005, Vol 54, Num 1, pp 441-444, issn 0007-8506, 4 p.Conference Paper

Similarity based system reconfiguration by fuzzy classification and hierarchical interpolate fuzzy reasoningKOVACS, S.Lecture notes in computer science. 1999, pp 12-19, issn 0302-9743, isbn 3-540-66050-XConference Paper

Optimization of the Multi-Spectral Euclidean Distance calculation for FPGA-based spaceborne systemsCRISTO, Alejandro; FISHER, Kevin; PEREZ, Rosa M et al.Aerospace science and technology (Imprimé). 2014, Vol 32, pp 1-9, issn 1270-9638, 9 p.Article

FPGA Based System for Open, Short, and RC Impedance MeasurementNEWMAN, Kimberly E.IEEE transactions on advanced packaging. 2010, Vol 33, Num 1, pp 147-152, issn 1521-3323, 6 p.Article

Reconfigurable adaptive FEC system based on reed-solomon code with interleavingSHIMIZU, Kazunori; TOGAWA, Nozomu; IKENAGA, Takeshi et al.IEICE transactions on information and systems. 2005, Vol 88, Num 7, pp 1526-1537, issn 0916-8532, 12 p.Article

Data multicasting procedure for increasing configuration speed of coarse grain reconfigurable devicesTUNBUNHENG, Vasutan; SUZUKI, Masayasu; AMANO, Hideharu et al.IEICE transactions on information and systems. 2007, Vol 90, Num 2, pp 473-481, issn 0916-8532, 9 p.Article

Méthodologie dédiée aux applications parallèles sur plateforme reconfigurable dynamiquement = Design methodology for parallel applications on dynamically reconfigurable platformFOUCHER, Clément; MULLER, Fabrice; GIULIERI, Alain et al.TSI. Technique et science informatiques. 2013, Vol 32, Num 2, pp 253-280, issn 0752-4072, 28 p.Article

Hydrodynamically driven docking of blocks for 3D fluidic assemblyKALONTAROV, Michael; TOLLEY, Michael T; LIPSON, Hod et al.Microfluidics and nanofluidics (Print). 2010, Vol 9, Num 2-3, pp 551-558, issn 1613-4982, 8 p.Article

A graph covering algorithm for a coarse grain reconfigurable systemYUANQING GUO; SMIT, Gerard J. M; BROERSMA, Hajo et al.ACM SIGPLAN notices. 2003, Vol 38, Num 7, pp 199-208, issn 1523-2867, 10 p.Conference Paper

A Retargetable Compiler Based on Graph Representation for Dynamically Reconfigurable Processor ArraysTUNBUNHENG, Vasutan; AMANO, Hideharu.IEICE transactions on information and systems. 2008, Vol 91, Num 11, pp 2655-2665, issn 0916-8532, 11 p.Article

Hybrid pattern BIST for low-cost core testing using embedded FPGA coreZENG, Gang; ITO, Hideo.IEICE transactions on information and systems. 2005, Vol 88, Num 5, pp 984-992, issn 0916-8532, 9 p.Article

Reconfigurable turbo decoding for 3G applicationsCHAIKALIS, Costas; NORAS, James M.Signal processing. 2004, Vol 84, Num 10, pp 1957-1972, issn 0165-1684, 16 p.Article

A novel and efficient routing architecture for multi-FPGA systemsKHALID, M. A. S; ROSE, J.IEEE transactions on very large scale integration (VLSI) systems. 2000, Vol 8, Num 1, pp 30-39, issn 1063-8210Article

Testing configurable LUT-based FPGA'sWEI KANG HUANG; MEYER, F. J; CHEN, X.-T et al.IEEE transactions on very large scale integration (VLSI) systems. 1998, Vol 6, Num 2, pp 276-283, issn 1063-8210Conference Paper

A two-level reconfigurable architecture for digital signal processing : On VLSI design and testMYJAK, M. J; DELGADO-FRIAS, J. G.Microelectronic engineering. 2007, Vol 84, Num 2, pp 244-252, issn 0167-9317, 9 p.Article

Exploration de l'espace de conception des architectures reconfigurablesBOSSUET, Lilian; GOGNIAT, Guy; PHILIPPE, Jean-Luc et al.TSI. Technique et science informatiques. 2006, Vol 25, Num 7, pp 921-946, issn 0752-4072, 26 p.Article

Instruction-Based Voltage Scaling for Power Reduction in SIMD MPSoCsMAJZOUB, Sohaib.Journal of low power electronics (Print). 2011, Vol 7, Num 2, pp 141-147, issn 1546-1998, 7 p.Article

Intégration de la synthèse de contrôleurs discrets dans un langage de programmationDELAVAL, Gwenaël; RUTTEN, Eric; MARCHAND, Hervé et al.Journal européen des systèmes automatisés. 2011, Vol 45, Num 1-3, pp 125-140, issn 1269-6935, 16 p.Conference Paper

Enhancement of Adaptability of Parallel Kinematic Machines With an Adjustable PlatformBI, Z. M; KANG, B.Journal of manufacturing science and engineering. 2010, Vol 132, Num 6, issn 1087-1357, 061016.1-061016.9Article

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