kw.\*:("RESEAU LOGIQUE ITERATIF")
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A TESTABLE DESIGN OF ITERATIVE LOGIC ARRAYSPARTHASARATHY R; REDDY SM.1981; IEEE TRANS. CIRCUITS SYST.; ISSN 0098-4094; USA; DA. 1981; VOL. 28; NO 11; PP. 1037-1045; BIBL. 11 REF.Article
DESIGN OF EASILY TESTABLE BIT-SLICED SYSTEMSTHIRUMALAI SRIDHAR; HAYES JP.1981; IEEE TRANS. CIRCUITS SYST.; ISSN 0098-4094; USA; DA. 1981; VOL. 28; NO 11; PP. 1047-1058; BIBL. 18 REF.Article