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HIGH-SPEED PROGRAMMABLE LOGIC ARRAY ADDERSWEINBERGER A.1979; I.B.M. J. RES.; USA; DA. 1979; VOL. 23; NO 2; PP. 163-178; BIBL. 8 REF.Article
STRUCTURED LOGIC DESIGN OF INTEGRATED CIRCUITS USING THE STORAGE/LOGIC ARRAY (SLA)SMITH KF; CARTER TM; HUNT CE et al.1982; IEEE TRANS. ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 4; PP. 765-776; BIBL. 18 REF.Article
NOUVEAUX PRODUITS DE LA MICROELECTRONIQUELOSCH F.1979; NACHR. ELEKTRON.; DEU; DA. 1979; VOL. 33; NO 2; PP. 50-52Article
COMPARISON OF LOGIC FUNCTION REALIZATION METHODS.HALTSONEN S.1977; ACTA POLYTECH. SCAND., ELECTR. ENGNG; SUEDE; DA. 1977; NO 41; PP. 1-22; BIBL. 1 P. 1/2; ISBN 9516660959Serial Issue
Un système de CAO pour la description et la simulation d'automates logiquesDABRIOU, R; LE BARON, J. P; BRIE, C et al.International journal of modelling & simulation. 1984, Vol 4, Num 1, pp 42-48, issn 0228-6203Article
Function symmetries and decoded-PLA realizationEKTARE, A. B; AL-SHEAKHLY, M. K. H.Computers & electrical engineering. 1988, Vol 14, Num 3-4, pp 137-150, issn 0045-7906Article
New logic array concept with high flexibilityBROCKMANN, W; VOGT, H; WEISS, R et al.Electronics Letters. 1985, Vol 21, Num 20, pp 891-892, issn 0013-5194Article
PLA folding algorithm from compatibility relationsBISWAS, N. N.Electronics Letters. 1985, Vol 21, Num 21, pp 984-986, issn 0013-5194Article
PLD based Arabic alphanumeric dot matrix decoderALSUWAILEM, A. M.International journal of electronics. 1995, Vol 78, Num 2, pp 239-245, issn 0020-7217Article
Commande par trajectoire optimale de convertisseurs à résonance série: conception d'un automate de commande rapprochée intégré = Optimal trajectory control of series resonant converter. Implementation of a nested-control integrated automatonBOYER, M; HAPIOT, J. C; CHERON, Y et al.Journal de physique. III (Print). 1995, Vol 5, Num 6, pp 727-741, issn 1155-4320Conference Paper
Reprogrammable FPLA with universal test setRAJSUMAN, R; MALAIYA, Y. K; JAYASUMANA, A. P et al.IEE proceedings. Part E. Computers and digital techniques. 1990, Vol 137, Num 6, pp 437-441, issn 0143-7062Article
Résolution à l'aide de circuits combinatoires programmables d'un système logique décrit par un graphe d'état = Resolution with combinatory programmable circuits of a logical circuit described by a state graphAUMIAUX, Michel.1984, 185 pThesis
Field programmable gate arrays in spaceFERNANDEZ-LEON, Agustin.IEEE instrumentation & measurement magazine. 2003, Vol 6, Num 4, pp 42-48, issn 1094-6969, 7 p.Article
Tradeoff literals against support for logic synthesis of LUT-based FPGAsLU, A; DAGLESS, E; SAUL, J et al.IEE proceedings. Computers and digital techniques. 1996, Vol 143, Num 2, pp 111-119, issn 1350-2387Article
Absolute minimization of completely specified switching functionsSUNG JE HONG; MUROGA, S.IEEE transactions on computers. 1991, Vol 40, Num 1, pp 53-65, issn 0018-9340, 13 p.Article
Concurrent error detection in highly structured logic arraysFUCHS, W. K; CHEN, C.-Y. R; ABRAHAM, J. A et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 4, pp 583-594, issn 0018-9200Article
Using programmable controllers for sequential systems with random inputsPESSEN, D. W.Proceedings of the Institution of Mechanical Engineers. Part C. Mechanical engineering science. 1987, Vol 201, Num 4, pp 245-249, issn 0263-7154Article
An alterable programmable logic arrayMARCHAND, J. F. P.IEEE journal of solid-state circuits. 1985, Vol 20, Num 5, pp 1061-1066, issn 0018-9200Article
Fault equivalence in PLAs and prevention designLIU, B.-D; SHAW, G.-T.Electronics Letters. 1990, Vol 26, Num 23, pp 1925-1926, issn 0013-5194Article
Three-step heuristic algorithm for optimal PLA column foldingYANG, Y.-Y; KYUNG, C.-M.Electronics Letters. 1988, Vol 24, Num 17, pp 1088-1090, issn 0013-5194Article
Built in test of folded PLAsFERNANDES, A. O; COURTOIS, B.Rapport de recherche - IMAG. 1988, issn 0750-7380, 23 p.Report
On the design of a redundant programmable logic array (RPLA)CHIN-LONG WEY; MAN-KUAN VAI; LOMBARDI, F et al.IEEE journal of solid-state circuits. 1987, Vol 22, Num 1, pp 114-117, issn 0018-9200Article
Interval-graph-based PLA foldingQINGJIAN YU; WING, O.Integration (Amsterdam). 1985, Vol 3, Num 1, pp 33-48, issn 0167-9260Article
On the implementation of sequential circuits with PLA modulesACHA, J. I; CALVO, J.IEE proceedings. Part E. Computers and digital techniques. 1985, Vol 132, Num 5, pp 246-250, issn 0143-7062Article
PLA implementation of k-out-of-n code TSC checkerBOSE, B; DER JEILIN.IEEE transactions on computers. 1984, Vol 33, Num 6, pp 583-588, issn 0018-9340Article