Pascal and Francis Bibliographic Databases

Help

Search results

Your search

kw.\*:("Random access memory")

Document Type [dt]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Publication Year[py]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Discipline (document) [di]

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Language

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Author Country

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Origin

A-Z Z-A Frequency ↓ Frequency ↑
Export in CSV

Results 1 to 25 of 4818

  • Page / 193
Export

Selection :

  • and

Low-temperature operation of silicon dynamic random-access memoriesWYNS, P; ANDERSON, R. L.I.E.E.E. transactions on electron devices. 1989, Vol 36, Num 8, pp 1423-1428, issn 0018-9383, 6 p.Article

Dual-ported memorySCAYSBROOK, F. F.Review of scientific instruments. 1986, Vol 57, Num 1, pp 122-123, issn 0034-6748Article

Interfacing multi-processors using devices with dual-port RAMGONZALES, D. R.Microelectronics. 1985, Vol 16, Num 3, pp 5-12, issn 0026-2692Article

All points addressable raster display memoryMATICK, R; LING, D. T; GUPTA, S et al.IBM journal of research and development. 1984, Vol 28, Num 4, pp 379-392, issn 0018-8646Article

A 128K×8 70-MHz multiport video RAM with auto register reload and 8×4 block WRITE featurePINKHAM, R; RUSSELL, D; GUILLEMAUD, A et al.IEEE journal of solid-state circuits. 1988, Vol 23, Num 5, pp 1133-1139, issn 0018-9200Article

An experimental 256Mb non-volatile DRAM with cell plate boosted programming techniqueAHN, J-H; HONG, S-H; CHOI, J-H et al.IEEE International Solid-State Circuits Conference. 2004, pp 42-43, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 500MHz multi-banked compilable DRAM macro with direct write and programmable pipeliningBARTH, J; ANAND, D; DREIBELBIS, J et al.IEEE International Solid-State Circuits Conference. 2004, pp 204-205, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 0.6V 205MHz 19.5ns tRC 16Mb embedded DRAMHARDEE, K; JONES, F; TANIGUCHI, K et al.IEEE International Solid-State Circuits Conference. 2004, pp 200-201, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 1.6Gb/s/pin double-data-rale SDRAM with wave-pipelined CAS latency controlLEE, Sang-Bo; JANG, Seong-Jin; HEO, Hyoung-Jo et al.IEEE International Solid-State Circuits Conference. 2004, pp 210-211, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

A 312MHz 16Mb random-cycle embedded DRAM macro with 73μW power-down mode for mobile applicationsMORISHITA, Fukashi; HAYASHI, Isamu; SHINKAWATA, Hiroki et al.IEEE International Solid-State Circuits Conference. 2004, pp 202-203, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

An 800MHz embedded DRAM with a concurrent refresh modeKIRIHATA, Toshiaki; PARRIES, Paul; WORDEMAN, Matt et al.IEEE International Solid-State Circuits Conference. 2004, pp 206-207, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

Architecture and circuit techniques for a reconfigurable memory blockKEN MAI; HO, Ron; ALON, Elad et al.IEEE International Solid-State Circuits Conference. 2004, pp 500-501, isbn 0-7803-8267-6, 2Vol, 2 p.Conference Paper

THE EFFECT OF PARASITIC CAPACITANCES ON THE CIRCUIT SPEED OF GAAS MESFET RING OSCILLATORSCHANG CTM; NAMORDI MR; WHITE WA et al.1982; IEEE TRANSACTIONS ON ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 11; PP. 1805-1809; BIBL. 8 REF.Article

A 32K ASIC synchronous RAM using a two-transistor basic cellYUEN, A; TSAO, P; YIN, P et al.IEEE journal of solid-state circuits. 1989, Vol 24, Num 1, pp 57-61, issn 0018-9200, 5 p.Article

Performance modeling of resonant tunneling-based random-access memoriesHUI ZHANG; MAZUMDER, Pinaki; LI DING et al.IEEE transactions on nanotechnology. 2005, Vol 4, Num 4, pp 472-480, issn 1536-125X, 9 p.Article

Resistive-Memory EmbeddedKIM, Sungho; CHOI, Sung-Jin; CHOI, Yang-Kyu et al.I.E.E.E. transactions on electron devices. 2009, Vol 56, Num 11, pp 2670-2674, issn 0018-9383, 5 p.Article

Logic based embedded dram technologiesMALLARDEAU, Catherine.Proceedings - Electrochemical Society. 2003, pp 133-135, issn 0161-6374, isbn 1-56677-376-8, 3 p.Conference Paper

Superior bipolar resistive switching characteristics of Cu-TiO2 based RRAM cellsHUANG, Yu-Chih; LIN, Huan-Min; CHENG, Huang-Chung et al.International journal of nanotechnology. 2014, Vol 11, Num 1-4, pp 156-166, issn 1475-7435, 11 p.Conference Paper

Programmable at-speed array and functional BIST for embedded DRAM LSIKUME, Masaji; UEHARA, Katsutoshi; ITAKURA, Minoru et al.International Test Conference. 2004, pp 988-996, isbn 0-7803-8580-2, 1Vol, 9 p.Conference Paper

At-speed interconnect test and diagnosis of external memories on a systemKIM, Heon C; JUN, Hong-Shin; XINLI GU et al.International Test Conference. 2004, pp 156-162, isbn 0-7803-8580-2, 1Vol, 7 p.Conference Paper

A new single-ended SRAM cell with write-assistHOBSON, Richard F.IEEE transactions on very large scale integration (VLSI) systems. 2007, Vol 15, Num 2, pp 173-181, issn 1063-8210, 9 p.Article

A 130nm 1.1V 143MHz SRAM-like. Embedded DRAM COMPILER with dual asymmetric bit line sensing scheme and quiet unselected IO schemeNOH, K. J; CHOI, Y. J; JOO, J. D et al.Symposium on VLSI Circuits. 2003, pp 190-191, isbn 0-7803-8287-0, 1Vol, 2 p.Conference Paper

A comparative study of the DRAM leakage mechanism for planar and recessed channel MOSFETsMYOUNG JIN LEE; BAEK, Chang-Ki; PARK, Sooyoung et al.Solid-state electronics. 2009, Vol 53, Num 9, pp 998-1000, issn 0038-1101, 3 p.Article

A REVIEW OF RAM TESTING METHODOLOGICSCORSI A; MORANDI C.1983; MICROELECTRONICS; ISSN 0026-2692; GBR; DA. 1983; VOL. 14; NO 2; PP. 55-71; BIBL. 29 REF.Article

MINIATURIZATION DEGREE OF DYNAMIC MOS RAM CELLS WITH READOUT SIGNAL GAINTSUCHIYA T; NAKAJIMA S.1982; IEEE TRANSACTIONS ON ELECTRON DEVICES; ISSN 0018-9383; USA; DA. 1982; VOL. 29; NO 11; PP. 1713-1717; BIBL. 6 REF.Article

  • Page / 193